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CY74FCT377ATQCTTIN/a4avaiOctal D-Type Flip-Flops with Enable
CY74FCT377ATSOCN/a1000avaiOctal D-Type Flip-Flops with Enable
CY74FCT377ATSOCCYPN/a1000avaiOctal D-Type Flip-Flops with Enable


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CY74FCT377ATQCT-CY74FCT377ATSOC
Octal D-Type Flip-Flops with Enable
Significantly Improved Noise
Characteristics
Ioff Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Fully Compatible With TTL Input and
Output Logic Levels
Clock Enable for Address and Data
Synchronization Application
Eight Edge-Triggered D-Type Flip-Flops CY54FCT377T
– 32-mA Output Sink Current
– 12-mA Output Source Current
CY74FCT377T
– 64-mA Output Sink Current
– 32-mA Output Source Current
description

The ’FCT377T devices have eight triggered D-type flip-flops with individual data (D) inputs. The common
buffered clock (CP) inputs load all flip-flops simultaneously when the clock-enable (CE) input is low. The register
is fully edge triggered. The state of each D input at one setup time before the low-to-high clock transition is
transferred to the corresponding flip-flop output (O). CE must be stable only one setup time prior to the
low-to-high clock transition for predictable operation.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54FCT377T... L PACKAGE
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13
GND6423 CE
GND65
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