CY74FCT373ATQCT ,Octal Transparent D-Type Latches with 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CY74FCT373ATSOC ,Octal Transparent D-Type Latches with 3-State Outputslogic diagram (positive logic)1OE11LECP2Q O03DD0To Seven Other Channels2POST OFFICE BOX 655303 • DA ..
CY74FCT373CTSOC , 8-BIT LATCHES WITH 3-STATE OUTPUTS
CY74FCT373TSOC ,Octal Transparent D-Type Latches with 3-State OutputsCY54FCT373T, CY74FCT373T 8-BIT LATCHESWITH 3-STATE OUTPUTSSCCS021B – MAY 1994 – REVISED OCTOBER 20 ..
CY74FCT374ATPC ,Octal Transparent D-Type Latches with 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CY74FCT374TQCT ,Octal Transparent D-Type Latches with 3-State OutputsCY54FCT374T, CY74FCT374T 8-BIT REGISTERSWITH 3-STATE OUTPUTSSCCS022A – MAY 1994 – REVISED OCTOBER ..
D20LC20U , Super Fast Recovery Rectifiers(200V 20A)
D20LC20U , Super Fast Recovery Rectifiers(200V 20A)
D20XB80 , General Purpose Rectifiers(800V 20A)
D20XB80 , General Purpose Rectifiers(800V 20A)
D2212 , METAL GATE RF SILICON FET
D2213 , METAL GATE RF SILICON FET
CY74FCT373ATQCT-CY74FCT373ATSOC-CY74FCT373TSOC
Octal Transparent D-Type Latches with 3-State Outputs
Significantly Improved Noise
Characteristics Ioff Supports Partial-Power-Down Mode
Operation ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101) Matched Rise and Fall Times Fully Compatible With TTL Input and
Output Logic Levels 3-State Outputs CY54FCT373T
– 32-mA Output Sink Current
– 12-mA Output Source Current CY74FCT373T
– 64-mA Output Sink Current
– 32-mA Output Source Current
descriptionThe ’FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the
latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup
times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE)
input is low. When OE is high, the bus output is in the high-impedance state. In this mode, data can be entered
into the latches.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.023
GND754
