CY74FCT273CTSOC ,Octal D-Type Flip-Flops with ClearCY54FCT273T, CY74FCT273T 8-BIT REGISTERS SCCS020A – MARCH 1995 – REVISED OCTOBER 2001CY54FCT273T . ..
CY74FCT2827ATQCT ,10-Bit Buffers/Drivers with 3-State Outputs and Series Damping ResistorsCY74FCT2827T 10-BIT BUFFERWITH 3-STATE OUTPUTSSCCS045A – MAY 1994 – REVISED SEPTEMBER 2001Q PACKAG ..
CY74FCT2827CTQCT ,10-Bit Buffers/Drivers with 3-State Outputs and Series Damping Resistorsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CY74FCT373ATQCT ,Octal Transparent D-Type Latches with 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
CY74FCT373ATSOC ,Octal Transparent D-Type Latches with 3-State Outputslogic diagram (positive logic)1OE11LECP2Q O03DD0To Seven Other Channels2POST OFFICE BOX 655303 • DA ..
CY74FCT373CTSOC , 8-BIT LATCHES WITH 3-STATE OUTPUTS
D209L , High Voltage Fast-Switching NPN Power Transistor
D209L , High Voltage Fast-Switching NPN Power Transistor
D209L. , High Voltage Fast-Switching NPN Power Transistor
D20LC20U , Super Fast Recovery Rectifiers(200V 20A)
D20LC20U , Super Fast Recovery Rectifiers(200V 20A)
D20XB80 , General Purpose Rectifiers(800V 20A)
CY74FCT273CTSOC
Octal D-Type Flip-Flops with Clear
Significantly Improved Noise
Characteristics Ioff Supports Partial-Power-Down Mode
Operation Matched Rise and Fall Times ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101) Fully Compatible With TTL Input and
Output Logic Levels CY54FCT273T
– 32-mA Output Sink Current
– 12-mA Output Source Current CY74FCT273T
– 64-mA Output Sink Current
– 32-mA Output Source Current
descriptionThe ’FCT273T devices consist of eight
edge-triggered D-type flip-flops with individual
D inputs and Q outputs. The common
buffered-clock (CP) and master-reset (MR) inputs
load and reset all flip-flops simultaneously. These
devices are edge-triggered registers. The state of
each D input (one setup time before the
low-to-high clock transition) is transferred to the
corresponding flip-flop’s Q output. All outputs are
forced low by a low logic level on the MR input.
This device is fully specified for
partial-power-down applications using Ioff . The Ioffcircuitry disables the outputs, preventing
damaging current backflow through the device
when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CY54FCT273T... L PACKAGE
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GND751 MR
GND7
