CY74FCT2373CTSOC ,Octal D-Type Transparent Latches with 3-State Outputs and Series Damping Resistors CY74FCT2373T 8-BIT LATCHWITH 3-STATE OUTPUTSSCCS039B – SEPTEMBER 1994 – REVISED OCTOBER 2001Q OR S ..
CY74FCT2374ATQCT , 8-BIT REGISTER WITH 3-STATE OUTPUTS
CY74FCT240ATQCT ,Octal Buffers/Drivers with 3-State OutputsCY54FCT240T, CY74FCT240T 8-BIT BUFFERS/LINE DRIVERSWITH 3-STATE OUTPUTSSCCS017A – MAY 1994 – REVIS ..
CY74FCT240ATSOC ,Octal Buffers/Drivers with 3-State OutputsCY54FCT240T, CY74FCT240T 8-BIT BUFFERS/LINE DRIVERSWITH 3-STATE OUTPUTSSCCS017A – MAY 1994 – REVIS ..
CY74FCT240ATSOC ,Octal Buffers/Drivers with 3-State Outputs/sc/package.FUNCTION TABLEINPUTSOUTPUTOOE OE DA BL L L HL LH LH H X ZH = High logic level, L = Low ..
CY74FCT240CTSOC , 8-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS
D1NL20 , Super Fast Recovery Rectifiers(200V 1A)
D1NL20 , Super Fast Recovery Rectifiers(200V 1A)
D1NL20U , Super Fast Recovery Rectifiers(200V 1A)
D1NL20U , Super Fast Recovery Rectifiers(200V 1A)
D1NL40 , Super Fast Recovery Rectifiers(400V 0.9 A)
D1NS4 , Schottky Rectifiers (SBD) (40V 1A)
CY74FCT2373CTSOC
Octal D-Type Transparent Latches with 3-State Outputs and Series Damping Resistors
OHEquivalent FCT Functions Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics Ioff Supports Partial-Power-Down Mode
Operation Matched Rise and Fall Times 3-State Outputs ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101) Fully Compatible With TTL Input and
Output Logic Levels 12-mA Output Sink Current
15-mA Output Source Current
descriptionThe CY74FCT2373T is an 8-bit, high-speed CMOS, TTL-compatible buffered latch with 3-state outputs that is
ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25-Ω termination
resistors at the outputs reduce system noise caused by reflections. The CY74FCT2373T can replace the
CY74FCT373T to reduce noise in an existing design.
When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the
required setup times are latched when LE transitions from high to low. Data appears on the bus when the
output-enable (OE) input is low. When OE is high, the bus output is in the high-impedance state. In this mode,
data can be entered into the latches.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.13
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