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CY29FCT52CTSOCTI/BBN/a20avai8-Bit Registered Transceiver


CY29FCT52CTSOC ,8-Bit Registered Transceiverlogic diagramCPACEAOEBCE CPA0 D Q B0 0 0A B1 D Q 11 1AB2 D Q 22 2A B3 3D Q3 3A B4 4D Q4 4A B55D Q5 ..
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CY2CC1810OI ,Low-voltage operationBlock Diagram Pin ConfigurationQ1OE#Q2 GND GND1 24Q10 Q12 23VDD VDDQ3 3 22VDDQ9 Q24 21OE# GND5 20Q4 ..
CY2CC1810OIT ,1:10 Clock Fanout Buffer with Output EnableBlock Diagram Pin ConfigurationQ1OE#Q2 GND GND1 24Q10 Q12 23VDD VDDQ3 3 22VDDQ9 Q24 21OE# GND5 20Q4 ..
CY2CC810OI ,1:10 Clock Fanout BufferCharacteristics @ 2.5V (see Figure 1)Parameter Description Conditions Min. Typ. Max. UnitI = –7 mA ..
CY2CC810OXIT ,1:10 Clock Fanout BufferCharacteristics @ 3.3 V (see Figure 5)Parameter Description Conditions Min Typ. Max UnitV Output hi ..
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CY29FCT52CTSOC
8-Bit Registered Transceiver
Significantly Improved Noise
Characteristics
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Ioff Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times Fully Compatible With TTL Input and
Output Logic Levels
64-mA Output Sink Current
32-mA Output Source Current
description

The CY29FCT52T has two 8-bit back-to-back registers that store data flowing in both directions between two
bidirectional buses. Separate clock, clock enable, and 3-state output-enable signals are provided for each
register. Both A outputs and B outputs are specified to sink 64 mA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
PIN DESCRIPTION

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.41
OEB
CPA
CEA
GND52
OEA
CPB
CEB
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