CY29FCT520CTSOC ,Multi-Level Pipeline Register CY29FCT520T MULTILEVEL PIPELINE REGISTERWITH 3-STATE OUTPUTSSCCS011C – MAY 1994 – REVISED NOVEMBER ..
CY29FCT52CTSOC ,8-Bit Registered Transceiverlogic diagramCPACEAOEBCE CPA0 D Q B0 0 0A B1 D Q 11 1AB2 D Q 22 2A B3 3D Q3 3A B4 4D Q4 4A B55D Q5 ..
CY29FCT818CTPC , Diagnostic Scan Register
CY2CC1810OI ,Low-voltage operationBlock Diagram Pin ConfigurationQ1OE#Q2 GND GND1 24Q10 Q12 23VDD VDDQ3 3 22VDDQ9 Q24 21OE# GND5 20Q4 ..
CY2CC1810OIT ,1:10 Clock Fanout Buffer with Output EnableBlock Diagram Pin ConfigurationQ1OE#Q2 GND GND1 24Q10 Q12 23VDD VDDQ3 3 22VDDQ9 Q24 21OE# GND5 20Q4 ..
CY2CC810OI ,1:10 Clock Fanout BufferCharacteristics @ 2.5V (see Figure 1)Parameter Description Conditions Min. Typ. Max. UnitI = –7 mA ..
D051212T-1W , 1W, FIXED INPUT, ISOLATED & UNREGULATED TWIN OUTPUT ULTRAMINIATURE SMD PACKAGE DC-DC CONVERTER
D051212T-2W , TWIN OUTPUT ULTRAMINIATURE SMD PACKAGE
D051515ND-1W , TWIN OUTPUT DC-DC CONVERTER
D051515NS-1W , TWIN OUTPUT DC-DC CONVERTER
D051515T-1W , 1W, FIXED INPUT, ISOLATED & UNREGULATED TWIN OUTPUT ULTRAMINIATURE SMD PACKAGE DC-DC CONVERTER
D051515T-2W , TWIN OUTPUT ULTRAMINIATURE SMD PACKAGE
CY29FCT520CTSOC
Multi-Level Pipeline Register
Significantly Improved Noise
Characteristics Ioff Supports Partial-Power-Down Mode
Operation Matched Rise and Fall Times Fully Compatible With TTL Input and
Output Logic Levels ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101) Single- and Dual-Pipeline Operation Modes Multiplexed Data Inputs and Outputs CY29FCT520T
– 64-mA Output Sink Current
32-mA Output Source Current CY29FCT520ATDMB, CY29FCT520BTDMB
– 32-mA Output Sink Current
12-mA Output Source Current 3-State Outputs
descriptionThe CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1,
and B2, which are configured by the instruction inputs I0, I1 as a single four-level pipeline or as two two-level
pipelines. The contents of any register can be read at the multiplexed output at any time by using the
multiplex-selection controls (S0 and S1).
The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input.
Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2
selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.
In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1.
This device is fully specified for partial-power-down applications using Ioff . The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.36
CLK
GND1257
