CS4103VHG ,IEEE P1394a Physical Layer DeviceTable of Contents1.0 ArchitecturalOverview.. 31.1 LINK INTERFACE ... ... ... ... .... ... ... ... . ..
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CS-4121 ,Low Voltage Precision Air-Core Tach/Speedo Drivertachometer or speedometer. The CS4121 takes a speed sensor inputand generates sine and cosine relat ..
CS4121EDWF20 , Low Voltage Precision Air-Core Low Voltage Precision Air-Core
CS4122XDWF24 ,Triple Air-Core Gauge Driver with Serial Input BusELECTRICAL CHARACTERISTICS (−40°C ≤ T ≤ 105°C, 7.5 V ≤ V ≤ 14 V, 4.5 V ≤ V ≤ 5.5 V;A BB CCunless o ..
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CX9210-VNG ,Geode Graphics Companion DSTN ControllerFunctional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CXA1003 , LOW POWER FM IF AMPLIFIER
CXA1003 , LOW POWER FM IF AMPLIFIER
CXA1003BM , LOW POWER FM IF AMPLIFIER
CXA1003BN , LOW POWER FM IF AMPLIFIER
CXA1003BN , LOW POWER FM IF AMPLIFIER
CS4103VHG
IEEE P1394a Physical Layer Device
ode™
EEE
General DescriptionThe National Semiconductor® Geode™ CS4103isa three
port 400 Mbit/sec IEEE 1394 Physical Layer (PHY) device.
The CS4103 compliesto revision 2.0of the P1394a specifi-
cation. The deviceisathreeport implementationofareus-
able cell design scalable from oneto sixteen ports.
The CS4103 supportsallof the P1394a enhancements
including connection debounce, arbitrated reset, ack-accel-
erated arbitration, fly-by concatenation, multi-speed packet
concatenation, PHY pinging, priority arbitration, and Sus-
pend/Resume operation.It also implements the standard
PHY-Link interface definedin IEEE specification 1394-1995
and updatedin the P1394a specificationfor direct connec-
tion with the Geode CS4210 IEEE 1394 Open Host Con-
troller Interface (OHCI) device. The interface can operatein
either director isolated mode and supports single capacitor
isolation with bus hold inputs.
The CS4103 providesa complete PHY solution including
all bias generation, differential line drivers and receivers,
single ended comparatorsfor speed signaling, speed sig-
naling current sources, bias detect, and connect detect cir-
cuitry per port.It includes data and strobe encoding/
decoding functionsas wellasa re-time FIFOto synchro-
nize the receive datato the local clock domain. The
CS4103 can receive and respondtoall the PHY packet
types definedin revision 2.0of the P1394a specification.It
also supports Suspend and Resume port states and con-
nect detect functions.
The CS4103 generates the internal clocks and the Link
SCLK (System Clock) basedona 24.576 MHz external
crystalora 24.576 MHz clock input. The CS4103 operates
froma single 3.3V supply and supports transfersat 98.304,
196.608, and 393.216 Mbit/sec, (usually referredtoas 100,
200, and 400 Mbit/sec respectively).
Features IEEE 1394 Physical Layer Device (PHY) compliant with
revision 2.0of P1394a includingall enhancements Scalable design from oneto sixteen ports Supports data ratesof 100, 200, and 400 Mbit/sec Single 3.3V supply operation Internal PLL generates SCLK andall internal clocks
froma single 24.576 MHz crystalor clock Includes Cable Power Sense comparatorfor cable
power monitoring Compatible with the Geode CS4210 OHCI Controller
and other IEEE 1394 OHCI devices Supports the isolated PHY-Link interface compliant with
1394-1995 and P1394a specifications Single capacitor bus hold isolation\ Power saving modes 80-pin TQFP (Thin Quad Flat Pack)
System Block Diagram
Geode™ CS4210
IEEE 1394
OHCI Controller
Geode™ CS4103
P1394a
Physical LayerEEPROM2C Interface
PCI Interface PHY-Link Interface
PCI Bus
IEEE 1394
Cable
Connectors
July 2000
Geode™ CS4103
IEEE P1394a Physical Layer Device
