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CR16HCS9VJE7-CR16MAS9VJE8-CR16MCS9VJE7-CR16MCS9VJE8
Family of 16-bit CAN-enabled CompactRISC Microcontrollers
InterruptControl
January 2002
CR16HCS5/CR16HCS9/CR16MAR5/CR16MAS5
CR16MAS9/CR16MBR5/CR16MCS5/CR16MCS9
Family of 16-bit CAN-enabled CompactRISC
Microcontrollers
1.0 General DescriptionThe family of 16-bit CompactRISC™ microcontroller is
based on a Reduced Instruction Set Computer (RISC) ar-
chitecture. The device operates as a complete microcom-
puter with all system timing, interrupt logic, flash program
memory or ROM memory, RAM, EEPROM data memory,
and I/O ports included on-chip. It is ideally suited to a wide
range of embedded controller applications because of its
high performance, on-chip integrated features and low
power consumption resulting in decreased system cost.
The device offers the high performance of a RISC architec-
ture while retaining the advantages of a traditional Com-
plex Instruction Set Computer (CISC): compact code, on-
chip memory and I/O, and reduced cost. The CPU uses a
three-stage instruction pipeline that allows execution of up
to one instruction per clock cycle, or up to 25 million in-
structions per second (MIPS) at a clock rate of 24 MHz.
The device contains a FullCAN class, CAN serial interface
for low/high speed applications with 15 orthogonal mes-
sage buffers, each supporting standard as well as extend-
ed message identifiers.
64k-Byte
Flash
Program
Memory
CR16CAN
Core Bus
Peripheral BusClock Generator
Slow Clk*
Processing
UnitI/O μWire/SPI 12-ch
Fast Clk
3k-BytePeripheralBusController
Power-on-Reset
2176-Byte
RAM EEPROMData
MIWU 2 Analog
Comparators
Timing and
Watchdog
Power
Manage-
ment
MFT
USART
CR16B
RISC Core8-bit A/D
ACCESS
bus
4x
VTU
Memory
Memory
FullCAN 2.0B
1.5k-Byte
ISP
Block Diagram
