CR14-MQP/1GE ,ISO14443-B Reader ICFeatures■ Single 5 V ±500 mV supply voltage■ SO16N package■ Contactless communication16– ISO14443 t ..
CR14-MQP-1GE ,ISO14443-B Reader ICAbsolute maximum ratings . 35Table 9. I²C AC measurement conditions . . . . . 36Table 10. ..
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CW025ACL-M , CW025 Triple-Output-Series Power Modules: 36 Vdc to 75 Vdc Input; 25W
CW201212-R82J , High Q Chip Inductors
CW252016-R39J , CW252016 Series - High Q Chip Inductors
CX06833-34 , V.92/V.34/V.32bis Modem in 144-Pin TQFP with Optional CX20442 Voice Codec
CX06833-42 , V.92/V.34/V.32bis Modem in 144-Pin TQFP with Optional CX20442 Voice Codec
CX06833-44 , V.92/V.34/V.32bis Modem in 144-Pin TQFP with Optional CX20442 Voice Codec
CR14-MQP/1GE-CR14-MQP-1GE-CR14-MQTP/1GE
ISO14443-B Reader IC
March 2010 Doc ID 11922 Rev 2 1/47
CR14ISO14443 type-B contactless coupler chip
with anti-collision and CRC management
Features Single 5 V ±500 mV supply voltage SO16N package Contactless communication ISO14443 type-B protocol 13.56MHz carrier frequency using an
external oscillator 106 Kbit/s data rate 36-byte input/output frame register Supports frame answer with/without
SOF/EOF CRC generation and check Automated ST anti-collision exchange I²C communication Two-wire I²C serial interface Supports 400 kHz protocol 3 chip enable pins Up to 8 CR14 connected on the same bus
Contents CR142/47 Doc ID 11922 Rev 2
Contents Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1 Oscillator (OSC1, OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Antenna output driver (RF OUT ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Antenna input filter (RFIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 T ransmitter reference voltage (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7 Chip enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8 Power supply (VCC , GND, GND_RF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CR14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.1 Parameter register (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Input/Output Frame Register (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Slot marker register (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CR14 I²C protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.1 I²C start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 I²C stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 I²C acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 I²C data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 I²C memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6 CR14 I²C write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7 CR14 I²C read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Applying the I²C protocol to the CR14 registers . . . . . . . . . . . . . . . . . 225.1 I²C parameter register protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 I²C input/output frame register protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 I²C slot marker register protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4 Addresses above location 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CR14 ContentsDoc ID 11922 Rev 2 3/47
CR14 ISO14443 type-B radio frequency data transfer . . . . . . . . . . . . . 266.1 Output RF data transfer from the CR14 to the PICC (request frame) . . . 26
6.2 T ransmission format of request frame characters . . . . . . . . . . . . . . . . . . 26
6.3 Request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4 Request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.5 Input RF data transfer from the PICC to the CR14 (answer frame) . . . . . 28
6.6 T ransmission format of answer frame characters . . . . . . . . . . . . . . . . . . . 28
6.7 Answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.8 Answer end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.9 T ransmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.10 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Tag access using the CR14 coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . 317.1 Standard TAG command access description . . . . . . . . . . . . . . . . . . . . . . 31
7.2 Anti-collision TAG sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Appendix A ISO14443 type B CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
List of tables CR144/47 Doc ID 11922 Rev 2
List of tablesTable 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. CR14 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Parameter register bits description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Input/output frame register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Slot marker register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. CR14 request frame character format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 9. I²C AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 10. I²C Input Parameters(1,2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 11. I²C DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12. I²C AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13. RFOUT AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 14. RFIN AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 15. SO16 narrow - 16 lead plastic small outline, 150 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 16. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
CR14 List of figuresDoc ID 11922 Rev 2 5/47
List of figuresFigure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. SO pin connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. CR14 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Maximum RL value versus bus capacitance (CBUS) for an I² C bus . . . . . . . . . . . . . . . . . . 11
Figure 6. I²C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. CR14 I²C write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. I²C polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. CR14 I²C read modes sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Host-to-CR14 transfer: I²C write to parameter register . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. CR14-to-host transfer: I²C random address read from parameter register . . . . . . . . . . . . 22
Figure 12. CR14-to-host transfer: I²C current address read from parameter register . . . . . . . . . . . . . 22
Figure 13. Host-to-CR14 transfer: I²C write to I/O frame register for ISO14443B . . . . . . . . . . . . . . . . 23
Figure 14. CR14-to-host transfer: I²C random address read from I/O frame register for ISO14443B 23
Figure 15. CR14-to-host transfer: I²C current address read from I/O frame register for ISO14443B . 24
Figure 16. Host-to-CR14 transfer: I²C write to slot marker register . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. CR14-to-host transfer: I²C random address read from slot marker register . . . . . . . . . . . 24
Figure 18. CR14-to-host transfer: I²C current address read from slot marker register . . . . . . . . . . . . 25
Figure 19. Wave transmitted using ASK modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 20. CR14 request frame character format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21. Request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 22. Request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 23. Wave received using BPSK sub-carrier modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 24. Answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 25. Answer end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 26. Example of a complete transmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 27. CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 28. Standard TAG command: request frame transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 29. Standard TAG command: answer frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 30. Standard TAG command: complete TAG access description. . . . . . . . . . . . . . . . . . . . . . . 32
Figure 31. Anti-collision ST short range memory sequence (1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 32. Anti-collision ST short range memory sequence continued . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 33. I²C AC testing I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 34. I²C AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 35. CR14 synchronous timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 36. SO16 narrow - 16 lead plastic small outline, 150 mils body width, Package outline . . . . . 42
Summary description CR146/47 Doc ID 11922 Rev 2
1 Summary descriptionThe CR14 is a contactless coupler that is compliant with the short range ISO14443 type-B
standard. It is controlled using the two wire I²C bus.
The CR14 generates a 13.56 MHz signal on an external antenna. Transmitted data are
modulated using Amplitude Shift Keying (ASK). Received data are demodulated from the
PICC (Proximity integrated Coupling Card) load variation signal, induced on the antenna,
using Bit Phase Shift Keying (BPSK) of a 847kHz sub-carrier. The Transmitted ASK wave is
10% modulated. The Data transfer rate between the CR14 and the PICC is 106 Kbit/s in
both transmission and reception modes.
The CR14 follows the ISO14443 type-B recommendation for Radio frequency power and
signal interface.
The CR14 is specifically designed for short range applications that need disposable and
reusable products.
The CR14 includes an automated anti-collision mechanism that allows it to detect and
select any ST short range memories that are present at the same time within its range. The
anti-collision mechanism is based on the STMicroelectronics probabilistic scanning method.
The CR14 provides a complete analog interface, compliant with the ISO14443 type-B
recommendations for Radio-Frequency power and signal interfacing. With it, any ISO14443
type-B PICC products can be powered and have their data transmission controlled via a
simple antenna.
The CR14 is fabricated in STMicroelectronics High Endurance Single Poly-silicon CMOS
technology.
The CR14 is organized as 4 different blocks (see Figure2): The I²C bus controller. It handles the serial connection with the application host. It is
compliant with the 400kHz I²C bus specification, and controls the read/write access to
all the CR14 registers. The RAM buffer. It is bi-directional. . It stores all the request frame Bytes to be
transmitted to the PICC, and all the received Bytes sent by the PICC on the answer
frame. The transmitter. It powers the PICCs by generating a 13.56MHz signal on an external
antenna. The resulting field is 10% modulated using ASK (amplitude shift keying) for
outgoing data. The receiver. It demodulates the signal generated on the antenna by the load variation
of the PICC. The resulting signal is decoded by a 847kHz BPSK (binary phase shift
keying) sub-carrier decoder.
The CR14 is designed to be connected to a digital host (Microcontroller or ASIC). This host
has to manage the entire communication protocol in both transmit and receive modes,
through the I²C serial bus.
CR14 Summary descriptionDoc ID 11922 Rev 2 7/47
Figure 1. Logic diagram Table 1. Signal names
Summary description CR14
8/47 Doc ID 11922 Rev 2
Figure 2. Logic block diagram
Figure 3. SO pin connections
CR14 Signal description
Doc ID 11922 Rev 2 9/47
2 Signal description
See Figure 1: Logic diagram, and Table 1: Signal names, for an overview of the signals
connected to this device.
2.1 Oscillator (OSC1, OSC2)
The OSC1 and OSC2 pins are internally connected to the on-chip oscillator circuit. The
OSC1 pin is the input pin, the OSC2 is the output pin. For correct operation of the CR14, it is
required to connect a 13.56MHz quartz crystal across OSC1 and OSC2. If an external clock
is used, it must be connected to OSC1 and OSC2 must be left open.
2.2 Antenna output driver (RF OUT)
The Antenna Output Driver pin, RFOUT, generates the modulated 13.56MHz signal on the
antenna. Care must be taken as it will not withstand a short-circuit.
RFOUT has to be connected to the antenna circuitry as shown in Figure 4: CR14 application
schematic The LRC antenna circuitry must be connected across the RFOUT pin and GND.
2.3 Antenna input filter (RFIN)
The antenna input filter of the CR14, RFIN, has to be connected to the external antenna
through an adapter circuit, as shown in Figure4.
The input filter demodulates the signal generated on the antenna by the load variation of the
PICC. The resulting signal is then decoded by the 847kHz BPSK decoder.
2.4 Transmitter reference voltage (V REF)
The T ransmitter Reference Voltage input, VREF , provides a reference voltage used by the
output driver for ASK modulation.
The T ransmitter Reference Voltage input should be connected to an external capacitor, as
shown in Figure4.
2.5 Serial clock (SCL)
The SCL input pin is used to strobe all I²C data in and out of the CR14. In applications
where this line is used by slave devices to synchronize the bus to a slower clock, the master
must have an open drain output, and a pull-up resistor must be connected from the Serial
Clock (SCL) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be
calculated).
In most applications, though, this method of synchronization is not employed, and so the
pull-up resistor is not necessary, provided that the master has a push-pull (rather than open
drain) output.
Signal description CR14
10/47 Doc ID 11922 Rev 2
2.6 Serial data (SDA)
The SDA signal is bi-directional. It is used to transfer I²C data in and out of the CR14. It is an
open drain output that may be wire-OR’ed with other open drain or open collector signals on
the bus. A pull-up resistor must be connected from Serial data (SDA) to VCC. (Figure5
indicates how the value of the pull-up resistor can be calculated).
2.7 Chip enable (E0, E1, E2)
The Chip Enable inputs E0, E1, E2 are used to set and reset the value on the three least
significant bits (b3, b2, b1) of the 7-bit I²C Device Select Code. They are used for hardwired
addressing, allowing up to eight CR14 devices to be addressed on the same I²C bus. These
inputs may be driven dynamically or tied to VCC or GND to establish the Device Select Code
(note that the VIL and VIH levels for the inputs are CMOS compatible, not TTL compatible).
When left open, E0, E1 and E2 are internally read at the logic level 0 due to the internal pull-
down resistors connected to each inputs.
2.8 Power supply (VCC , GND, GND_RF)
Power is supplied to the CR14 using the VCC, GND and GND_RF pins.
VCC is the Power Supply pin that supplies the power (+5V) for all CR14 operations.
The GND and GND_RF pins are ground connections. They must be connected together.
Decoupling capacitors should be connected between the VCC Supply Voltage pin, the GND
Ground pin and the GND_REF Ground pin to filter the power line, as shown in Figure4.
Figure 4. CR14 application schematic
CR14 Signal description
Doc ID 11922 Rev 2 11/47
Figure 5. Maximum RL value versus bus capacitance (CBUS) for an I² C bus
CR14 registers CR14
12/47 Doc ID 11922 Rev 2
3 CR14 registers
The CR14 chip coupler contains six volatile registers. It is entirely controlled, at both digital
and analog level, using the three registers listed below and shown in Table2: Parameter Register Input/Output Frame Register Slot Marker Register
The other 3 registers are located at addresses 02h, 04h and 05h. They are “ST Reserved”,
and must not be used in end-user applications.
In the I²C protocol, all data Bytes are transmitted Most Significant Byte first, with each Byte
transmitted Most significant bit first.
3.1 Parameter register (00h)
The Parameter Register is an 8-bit volatile register used to configure the CR14, and thus, to
customize the circuit behavior. The Parameter Register is located at the I²C address 00h
and it is accessible in I²C Read and Write modes. Its default value, 00h, puts the CR14 in
standard ISO14443 type-B configuration.
Table 2. CR14 control registers
Table 3. Parameter register bits description
CR14 CR14 registers
Doc ID 11922 Rev 2 13/47
3.2 Input/Output Frame Register (01h)
The Input/Output Frame Register is a 36-Byte buffer that is accessed serially from Byte 0
through to Byte 35 (see Table 4). It is located at the I²C address 01h.
The Input/Output Frame Register is the buffer in which the CR14 stores the data Bytes of
the request frame to be sent to the PICC. It automatically stores the data Bytes of the
answer frame received from the PICC. The first Byte (Byte 0) of the Input/Output Frame
Register is used to store the frame length for both transmission and reception.
When accessed in I²C Write mode , the register stores the request frame Bytes that are to
be transmitted to the PICC. Byte 0 must be set with the request frame length (in Bytes) and
the frame is stored from Byte 1 onwards. At the end of the transmission, the 16-bit CRC is
automatically added. After the transmission, the CR14 wait for the PICC to send back an
answer frame. When correctly decoded, the PICC answer frame Bytes are stored in the
Input/Output Frame Register from Byte 1 onwards. Byte 0 stores the number of Bytes
received from the PICC.
When accessed in I²C Read mode, the Input/Output Register sends back the last PICC
answer frame Bytes, if any, with Byte 0 transmitted first. The 16-bit CRC is not stored, and it
is not sent back on the I²C bus.
The Input/Output Frame Register is set to all 00h between transmission and reception. If
there is no answer from the PICC, Byte 0 is set to 00h. In the case of a CRC error, Byte 0 is
set to FFh, and the data Bytes are discarded and not appended in the register.
The CR14 Input/Output Frame Register is so designed as to generate all the ST short range
memory command frames. It can also generate all standardized ISO14443 type-B
command frames like REQB, SLOT-MARKER, ATTRIB, HALT , and get all the answers like
ATQB, or answer to ATTRIB. All ISO14443 type-B compliant PICCs can be accessed by the
CR14 provided that their data frame exchange is not longer than 35 Bytes in both request
and answer. RFU = Reserved for Future Use.
Table 3. Parameter register bits description (continued)
CR14 registers CR14
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3.3 Slot marker register (03h)
The slot Marker Register is located at the I²C address 03h. It is used to trigger an automated
anti-collision sequence between the CR14 and any ST short range memory present in the
electromagnetic field. With one I²C access, the CR14 launches a complete stream of
commands starting from PCALL16(), SLOT_MARKER(1), SLOT_MARKER(2) up to
SLOT_MARKER(15), and stores all the identified Chip_IDs into the Input/Output Frame
Register (I²C address 01h).
This automated anti-collision sequence simplifies the host software development and
reduces the time needed to interrogate the 16 slots of the STMicroelectronics anti-collision
mechanism.
When accessed in I²C Write mode, the Slot Marker Register starts generating the sequence
of anti-collision commands. After each command, the CR14 wait for the ST short range
memory answer frame which contains the Chip_ID. The validity of the answer is checked
and stored into the corresponding Status Slot Bit (Byte 1 and Byte 2 as described in
Table 5). If the answer is correct, the Status Slot Bit is set to ‘1’ and the Chip_ID is stored
into the corresponding Slot_Register. If no answer is detected, the Status Slot Bit is set to
‘0’, and the corresponding Slot_Register is set to 00h. If a CRC error is detected, the Status
Slot Bit is set to ‘0’, and the corresponding Slot_Register is set to FFh.
Each time the Slot Marker Register is accessed in I²C Write mode, Byte 0 of the
Input/Output Frame Register is set to 18, Bytes 1 and 2 provide Status Bits Slot information,
and Bytes 3 to 18 store the corresponding Chip_ID or error code.
The Slot Marker Register cannot be accessed in I²C Read mode. All the anti-collision data
can be accessed by reading the Input/Output Frame Register at the I²C address 01h.
Table 4. Input/output frame register description
Table 5. Slot marker register description
CR14 CR14 registers
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Table 5. Slot marker register description (continued)
CR14 I²C protocol description CR14
16/47 Doc ID 11922 Rev 2 CR14 I²C protocol description
The CR14 is compatible with the I²C serial bus memory standard, which is a two-wire serial
interface that uses a bi-directional data bus and serial clock.
The CR14 has a pre-programmed, 4-bit identification code, ’1010’ (as shown in Table6),
that corresponds to the I²C bus definition. With this code and the three Chip Enable inputs
(E2, E1, E0) up to eight CR14 devices can be connected to the I²C bus, and selected
individually.
The CR14 behaves as a slave device in the I²C protocol, with all CR14 operations
synchronized to the serial clock.
I²C Read and Write operations are initiated by a START condition, generated by the bus
master.
The START condition is followed by the Device Select Code and by a Read/Write bit (R/W).
It is terminated by an acknowledge bit. The Device Select Code consists of seven bits (as
shown in Table6): the Device Code (first four bits) plus three bits corresponding to the states of the three Chip Enable inputs, E2, E1 and
E0, respectively
When data is written to the CR14, the device inserts an acknowledge bit (9th bit) after the
bus master’s 8-bit transmission.
When the bus master reads data, it also acknowledges the receipt of the data Byte by
inserting an acknowledge bit (9th bit).
Data transfers are terminated by a STOP condition after an ACK for Write, or after a NoACK
for Read.
The CR14 supports the I²C protocol, as summarized in Figure6.
Any device that sends data on to the bus, is defined as a transmitter, and any device that
reads the data, as a receiver.
The device that controls the data transfer is known as the master, and the other, as the
slave. A data transfer can only be initiated by the master, which also provides the serial
clock for synchronization. The CR14 is always a slave device in all I²C communications. All
data are transmitted Most Significant Bit (MSB) first.
4.1 I²C start condition
START is identified by a High-to-Low transition of the Serial Data line, SDA, while the Serial
Clock, SCL, is stable in the High state. A START condition must precede any data transfer
command.
Table 6. Device select code
CR14 CR14 I²C protocol description
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The CR14 continuously monitors the SDA and SCL lines for a START condition (except
during Radio Frequency data exchanges), and will not respond unless one is sent.
4.2 I²C stop condition
STOP is identified by a Low-to-High transition of the Serial Data line, SDA, while the Serial
Clock, SCL, is stable in the High state.
A STOP condition terminates communications between the CR14 and the bus master.
A STOP condition at the end of an I²C Read command, after (and only after) a NoACK,
forces the CR14 into its stand-by state.
A STOP condition at the end of an I²C Write command triggers the Radio Frequency data
exchange between the CR14 and the PICC.
4.3 I²C acknowledge bit (ACK)
An acknowledge bit is used to indicate a successful data transfer on the I²C bus.
The bus transmitter, either master or slave, releases the Serial Data line, SDA, after sending
8 bits of data. During the 9th clock pulse the receiver pulls the SDA line Low to acknowledge
the receipt of the 8 data bits.
4.4 I²C data input
During data input, the CR14 samples the SDA bus signal on the rising edge of the Serial
Clock, SCL. For correct device operation, the SDA signal must be stable during the Low-to-
High Serial Clock transition, and the data must change only when the SCL line is Low.
CR14 I²C protocol description CR14
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Figure 6. I²C bus protocol
4.5 I²C memory addressing o start up communication with the CR14, the bus master must initiate a START condition.
Then, the bus master sends 8 bits (with the most significant bit first) on the Serial Data line,
SDA. These bits consist of the Device Select Code (7 bits) plus a RW bit.
According to the I²C bus definition, the seven most significant bits of the Device Select Code
are the Device T ype Identifier. For the CR14, these bits are defined as shown in Table6.
The 8th bit is the Read/Write bit (RW). It is set to ‘1’ for I²C Read, and to ‘0’ for I²C Write
operations.
If the data sent by the bus master matches the Device Select Code of a CR14 device, the
corresponding device returns an acknowledgment on the SDA bus during the 9th bit time.
The CR14 devices whose Device Select Codes do not correspond to the data sent,
generate a No-ACK. They deselect themselves from the bus and go into stand-by mode.
CR14 CR14 I²C protocol description
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4.6 CR14 I²C write operations
The bus master sends a START condition, followed by a Device Select Code and the R/W
bit set to ’0’. The CR14 that corresponds to the Device Select Code, acknowledges and
waits for the bus master to send the Byte address of the register that is to be written to. After
receipt of the address, the CR14 returns another ACK, and waits for the bus master to send
the data Bytes that are to be written.
In the CR14 I²C Write mode, the bus master may sends one or more data Bytes depending
on the selected register.
The CR14 replies with an ACK after each data Byte received. The bus master terminates
the transfer by generating a STOP condition.
The STOP condition at the end of a Write access to the Input/Output Frame Register causes
the Radio Frequency data exchange between the CR14 and the PICC to be started.
During the Radio Frequency data exchange, the CR14 disconnects itself from the I²C bus.
The time (tRFEX) needed to complete the exchange is not fixed as it depends on the PICC
command format. To know when the exchange is complete, the bus master uses an ACK
polling sequence as shown in Figure 8. It consists of the following: Initial condition: a Radio Frequency data exchange is in progress. Step 1: the master issues a START condition followed by the first Byte of the new
instruction (Device Select Code plus R/W bit). Step 2: if the CR14 is busy, no ACK is returned and the master goes back to Step 1. If
the CR14 has completed the Radio Frequency data exchange, it responds with an
ACK, indicating that it is ready to receive the second part of the next instruction (the
first Byte of this instruction being sent during Step 1).
Figure 7. CR14 I²C write mode sequence
CR14 I²C protocol description CR14
20/47 Doc ID 11922 Rev 2 o send a Read command, the bus master sends a START condition, followed by a Device
Select Code and the R/W bit set to ’1’.
The CR14 that corresponds to the Device Select Code acknowledges and outputs the first
data Byte of the addressed register. o select a specific register, a dummy Write command must first be issued, giving an
address Byte but no data Bytes, as shown in the bottom half of Figure 9. This causes the
new address to be stored in the internal address pointer, for use by the Read command that
immediately follows the dummy Write command.
In the I²C Read mode, the CR14 may read one or more data Bytes depending on the
selected register. The bus master has to generate an ACK after each data Byte to read all
the register data in a continuous stream. Only the last data Byte should not be followed by
an ACK. The master then terminates the transfer with a STOP condition, as shown in
Figure9.
CR14 CR14 I²C protocol description
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After reading each Byte, the CR14 waits for the master to send an ACK during the 9th bit
time. If the master does not return an ACK within this time, the CR14 terminates the data
transfer and switches to stand-by mode.
Figure 9. CR14 I²C read modes sequences
Applying the I²C protocol to the CR14 registers CR14
22/47 Doc ID 11922 Rev 2 Applying the I²C protocol to the CR14 registers
5.1 I²C parameter register protocol
Figure 10 shows how new data is written to the Parameter Register. The new value
becomes active after the I²C STOP condition.
Figure 11 shows how to read the Parameter Register contents. The CR14 sends and re-
sends the Parameter Register contents until it receives a NoACK from the I²C Host.
The CR14 supports the I²C Current Address and Random Address Read modes. The
Current Address Read mode can be used if the previous command was issued to the
register where the Read is to take place.
CR14 Applying the I²C protocol to the CR14 registers
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5.2 I²C input/output frame register protocol
Figure 13 shows how to store a PICC request frame command of N Bytes into the
Input/Output Frame Register.
After the I²C STOP condition, the request frame is RF transmitted in the ISO14443 type-B
format. The CR14 then waits for the PICC answer frame which will also be stored in the
Input/Output Frame Register. The request frame is over-written by the answer frame.
Figure 14 shows how to read an N-Byte PICC answer frame.
The two CRC Bytes generated by the PICC are not stored.
The CR14 continues to output data Bytes until a NoACK has been generated by the I²C
Host, and received by the CR14. After all 36 Bytes have been output, the CR14 “rolls over”,
and starts outputting from the start of the Input/Output Frame Register again.
The CR14 supports the I²C Current Address and Random Address Read modes. The
Current Address Read mode can be used if the previous command was issued to the
register where the Read is to take place.
Applying the I²C protocol to the CR14 registers CR14
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An I²C Write command to the Slot Marker Register generates an automated sixteen-
command loop (See Figure 16 for a description of the command).
All the answers from the ST short range memory devices that are detected, are written in
the Input/Output Frame Register.
Read from the I²C Slot Marker Register is not supported by the CR14. If the I²C Host tries to
read the Slot Marker Register, the CR14 will return the data value FFh in both Random
Address and Current Address Read modes until NoACK is generated by the I²C Host.
The result of the detection sequence is stored in the Input/Output Frame Register. This
Register can be read by the host by using I²C Random Address Read.
Figure 16. Host-to-CR14 transfer: I²C write to slot marker register
