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COP8720CN-COP8722CN
2.5 V to 6.0 V, single-chip microCMOS microcontroller
Z? Natiqnal .
Semiconductor
PRELIMINARY
CoP8720CfCOP8721C/COP8722C
Single-Chip microCMOS Microcontrollers
General Description
The COP8720CfCOP872tG/CDP8722C are members
of the COPSTM microcontroller family featuring on-chip
EEPROM modules. They are fully static parts, fabricated us-
ing doubltFntatal siiicon gate microCMOS technology. This
low cost microcontroller is a complete microcomputer con-
taining all system timing. interrupt logic, ROM, RAM, and
l/O necessary to implement dedicated control functions in a
variety of applications. Features include an 6-bit memory
mapped architecture. MICROWIRE/PLUSTM serial I/O, a
16-bit timer/counter with capture register and a multi-
sourced Interrupt. Each I/O pin has software selectable op-
tions to adapt the COP87200 to the specific application.
The part operates over a voltage range of 2.5V to 6.0V. High
throughput Is achieved with an efficient, regular instruction
set operating at a 1 microsecond per Instruction rate. The
COP6720 is totally compatible with the ROM based
copaaoc microcontroller. It serves as a form, fit and func-
tion emulator device for the COP820 microcontroller fam-
Features
I: Low Cost 8-bit CORE microcontroller
" Fully static CMOS
u 1 us instruction time (20 MHz clock)
I: Low current drain (2.2 mA at a pa instruction rate)
Low current static HALT mode (T ypicaily < 10 pA)
II Single supply operation: 2.5V to 6.0V
I: 1024 bytes EEPROM program memory
a 64 bytes of RAM
I: 64 bytes EEPHOM data memory
" 16-bit read/write timer operates in a variety of modes
- Timer with 16-bit auto reload register
- 16-bit externai event counter
- Timer with 16-bit capture register (selectabie edge)
tt Multi-source interrupt
- Reset master clear
- External Interrupt with selectable edge
- Timer interrupt or capture interrupt
- Software Interrupt
8-bit stack pointer (stack in RAM)
Powerful instruction set, most instructions single byte
BCD arithmetic instruction
MiCFtOWIFiE/PLUSTM serial I/O
28 pin package (optionally 24 or 20 pin package)
24 input/output pins
Software selectable " options (TFiI-STATEO. push-
pull, weak puII-up)
Schmitt trigger inputs on Port G
Form, fit and function EEPROM emulation device for
COP8200/COP821C/COP8220
" Fully supported by Nationai's MOLETM development
system
Block Diagram
E mm m an nun vac am
1024 l a " x ' - " x I l 1 l
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mom non L PORT I) PORT a mu TUDD/O108-1
FIGURE 1
OZZLBdOO/OlZLBdOO/OOZLBdOO
COP8720C/COP8721CICOP87226
Absolute Maximum Ratings
ll Mllltary/Attrospatm ttttere) devlcea are required,
please contact the National Semlconductor Sales
offlttttfDltttrittttttmt for availability and apeemeatlorta.
Supply Voltage (V00)
Voltage at any Pin
ESD Susceptibility (Note 4)
Total Current into VCC Pin (Source)
-0.3V to Vcc + 0.3V
Total Current outof GND Pin (Sink) 60 mA
Storage Temperature Range --65'C to + 140°C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electri-
cal speciiieations are not ensured when operating the de-
vice at absolute maximum ratings.
DC Electrical Characteristics -4tPC s TA g +690 uNessotherwisespeemed
Parameter Condmon Min Typ Max Units
Operating Voltage 2.5 6.0 V
Power Supply Ripple (Note 1) Peak to Peak 0.1 Voc V
Operating Voltage
during EEPROM Write (Note 7) 4.5 6.0 V
Supply Current (see page 10)
High Speed Mode. CKI = 20 MHz Vcc = 6V, tc = 1 ya 13 mA
Normal Mode, CKI = 5 MHz Voc = 6V, tc = 2 p.s 7 mA
Normal Mode, CKI == 2 MHz Voc = 2.5V, to = 5 ps 2 mA
(Note 2)
HALT Current Vcc = tN, CKI = OMHz <10 30 pA
(Note 3)
Input Levels
RE§ET. CKI
Logic High 0.9 Vcc V
Logic Low 0.1 Vcc V
All Other Inputs
Logic High 0.7 VCC V
Logic Low 0.2 Vcc V
Hr-z Input Leakage Vcc = 6.0V -2 + 2 WA
Input Pullup Current Vcc = 6.0V 40 250 WA
G Port Input Hysteresis 0.05 Vcc V
Output Current Levels
D Outputs
Source Vcc = 4.5V, VOH = 3.8V 0.4 mA
Vcc = 2.5V,VOH = 1.8V 0.2 mA
Sink Vcc = 4.5V, VOL == 1.0V 10 mA
Vcc = 2.5V, VOL = 0.4V 2.0 mA
All Others
Source (Weak Pull-Up) Vcc = 4.5V, VOH = 3.2V 10 100 pA
Vcc = 2.5V, Von == 1.8V 2.5 33 p.A
Source (Push-Pull Mode) Vcc = 4.5V, VOH = 3.8V 0.4 mA
Vcc = 2.5V, VOH = 1.8V 0.2 mA
Sink (Push-Pull Mode) Vcc = 4.5V, VOL = 0.4V 1.6 mA
Vcc = 2.5V, VOL = 0.4V 0.7 mA
TRI-STATE Leakage -2.0 + 2.0 pA
Allowable Sink/Source
Current Per Pin
D Outputs (Sink) 15 mA
All Others 3 mA
Maximum Input Current (Room Temp)
without Latchup (Note 5) 1 100 mA
RAM Retention Voltage, Vr 500 ns Rise and Fall Time (Min) 2.0 V
input Capacitance 7 pF
Load Capacitance on D2 1000 pF
AC Electrical Characteristics -40°c < TA < +as~c unless otherwise specified
Parameter Condltlon Mln Typ Max Units
Instruction Cycie Time (to)
High Speed Mode Voc te 4.5V 1 DC ps
(Div-by 20) 2.5V s; Vcc < 4.5V 2.5 DC ps
Normal Mode Vcc tt 4.5V 2 DC p.s
(Div-by 10) 2.5V I Vcc < 4.5V 5 DC us
RIC Osttillator Mode V00 2 4.5V 3 DC p.s
(Div-by 10)
2.5V g Vcc < 4.5V 7.5 DC p5
CKI Clock Duty Cycle fr = Max (+ 20 Mode) 33 66 %
(Note 6)
Rise Time (Note 6) fr = 20 MHz Ext Clock 12 ns
Fall Time (Note 6) fr = 20 MHz Ext Clock B ns
Inputs
Lamp VCC 2 4.5V 200 ns
2.5V 3 Vcc < 4.5V 500 ns
tHOLD Vcc 2 4.5V 60 ns
2.5V s Vcc < 4.5V 150 ns
Output Propagation Delay RL = 2.2K, A = 100 pF
tpm, two
SO, SK Vcc it 4.5V 0.7 JIS
2.5V Si Vcc < 4.5V 1.75 113
All Others Vcc 2 4.5V 1 us
2.5V s vcc < 4.5V 2.5 ps
MICROWIRETM Setup Time
MICROWIRE Hold Time
MICROWIRE Output Propagation 220 ns
Delay tUPD
Input Pulse Width
Interrupt Input High Time tC
Interrupt Input Low Time to
Timer Input High Time tc
Timer Input Low Time tC
Reset Pulse Width 1.0 ps
Not. 1: Rate ot voltage change must be less than 0.5V/ms.
N01. 2: Supply current is measured after running 2000 cycIes with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode wll stop CKI trom oscillating In the RC and the Crystal configurations. Test conditions: M inputs tied to 'hr, L and G ports are at
TRl-STATE and tied to ground. all outputs low and titett to ground.
Note 4: Human body model, 100 pF through 15000,
Not. 5: Excem pins Gs, ar, FTEEET
pins GB, RESET: + 60 mA
pin G7: -25 mA
Not- a: Paramem sampled but not 100% tested.
Not. r.. The temperature range tor write operation In 0'0 to 700
EEPROM Charattterlgtiett
Parameter Condition Mln Typ Max Unit-
EEPROM Write Cycle Time 4.5V s; vcc s 6.0V 15 20 25 ms
EEPROM Number of Writes 10000 Cycles
Vcc Level for Write Lock Out VLKo 3.9 4.4 V
Programming Voltage to WET Pin Vprg
4.5V S Vcc S 6.0V 11.5 12 12.5 v
OZZLBdOO/ OlZleOO/ 003181500
COP87206/COP8721C/COP87220
Timing Diagrams
TLIDD/9108-22
FIGURE 2. MlCROWIRE/PLUS Timing Diagram
Connection Diagrams
20-Pln Dual-in-Line Package 24.Pln Dual-In-Llne Package 28-Pln DuaI-ln-Llne Package
u/so-1 V 20 -c.s/no c4/so-1 V " -ca/no m/so-1 V " -cs/no
w/sx- l 19 -cz GS/SX- l 23 -tt2 cs/sx- 2 tt -e2
GB/SI-I ' 13 -trl GE/SI- 3 22 -t31 M/SQ- 3 " -c1
waxed t 17 40/1111 cv/oxo- 4 21 -G0/Wt c7/cxo- 4 25 -awt
cxl-s 15-11311 cn-s 20 -eftt cto-' 24 -EEs_n
'tT- s 15 -6tt0 voc- s " -tltR) voc- a 23 -tltil)
Lo-1 14-17 10-7 18-03 10-7 22-03
L1-8 13 -us 13-3 17-00 11-: 21-112
u-' 12 -u. L0-9 1s-L7 12-9 20 -o1
J- M) 11 -" 11-10 IS '-LF 13-10 19 -oo
1.2- 11 14 -L5 Lo- 11 " w-L?
TUDDt9t08-3 1.3- 12 13 -t.4 L1 - 12 t? -L6
Order Number COPB722CN L2- 13 " -u
See " Molded Package TL/DD/9108-4 L5- " 15 '-L4
Number N20A Order Number COP8721CN
See NS Molded Package rL/Dotmoa-s
Number N24A Order Number COP87200N
See NS Molded Package
Number N283
28-Pln PLCC
B a #,' 8
'fi',.-::,',:,,)':,''-'?,''',,,,,,-,
I I I I l I I
p" 4 3 2 1 28 27 26
CKI- 5 25 -GO/INT
Voc - s 24 - iitWt
I0 - 7 23 - tmo
11- 8 22 '-03
12 - 9 21 - 02
I3 - 10 20 - OI
L0 - 11 19 - D0
12 13 14 Mi 16 17 18
I I I I I I I
5 21 Cl y, I', 3 D
TLt9tVtrt08-24
Order Number COP87ZOCV
See NS PLCC Package
Number V28A
FIGURE 3
Connection Diagrams (Continued)
COP8722C COP8721C copenoc
PORT (z:za Pom I (rrrzan
yec-. PORT k::::::::::)
'CC, vcc- mm :21) vcc- PORT o d)
tttit-. PORT c a 'C, - "I' -
- PORT LHM PORT L (zzz)
gl kt tr- ttESO--
MiCROWlRE/PLUS PORT c 8 PORT e a
TLIDD/9108-6 mm mm
ttit) cxo
moaome/Pws MlCtt0UR0PL0s
TL/DO/9t08-7 TL/DDN10tr-8
FIGURE 3 (Continued)
Pin Descriptions
Vcc and GND are the power supply pins.
CKI is the clock input. This can come from an external
source, a RIC generated oscillator or a crystal (in conjunc-
tion with CKO). See Oscillator description.
REgET is the master reset input. See Reset description.
PORT I is a tour bit Hi-Z input port.
PORT L is an 8-bit I/O port.
There are two registers associated with each L I/O port: a
data register and a configuration register. Therefore, each L
UO bit can be individually configured under software control
as shown below:
Port L Port L Port L
Config. Data Setup
0 0 Hi-Z Input (T RI-STATE)
0 1 Input With Week PulI-Up
1 0 Push-Pull "0" Output
1 1 Push-Pull "I'' Output
Three data memory address locations are allocated for
these ports, one for data register. one for configuration reg-
ister and one for the input pins.
PORT G is an 8-bit port with 6 VO pins (GO-GN and 2 input
pins (66. " All eight G-pins have Schmitt Triggers on the
inputs. The G7 pin functions as an input pin under normal
operation and as the continue pin to exit the HALT mode.
There are two registers with each I/O port: a data register
and a configuration register. Therefore, each I/O bit can be
individually configured under software control as shown be.
Port G Port G Port G
Conflg. Data Setup
0 0 Hi-Z Input (T RI-STATE)
0 1 Input With Weak Puli-Up
1 0 Push-Pull "o" Output
1 1 Push-Pull "I" Output
Three data memory address locations are allocated for
these ports, one for data register, one for configuration reg-
ister and one for the input pins. Since G6 and G7 are input
only pins, any attempt by the user to set them up as outputs
by writing a one to the configuration register will be disre-
garded. Reading the GS and G7 configuration bits will
return zeros. Note that the chip will be placed in the HALT
mode by setting the G7 data bit.
Six bits of Port G have alternate features:
GO INTR (an external interrupt)
Ga TIO (timer/counter input/output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock l/O)
G6 Sl (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input (general purpose input)
Pins G1 and G2 currently do not have any alternate func-
tions.
PORT D is a four bit output port that is set high when
AES-ET goes low.
The D2 pin is sampled at reset. If it is held low at reset the
COP87200 enters the ROMIess mode of operation.
Functional Description
Figure , shows the block diagram of the internal architec-
ture. Data paths are illustrated in simplified form to depict
how the various logic elements communicate with each oth-
er in implementing the instruction set of the device.
ALU AND CPU REGISTERS
The ALU can do an 8-bit addition, subtraction, logical or
shift operation in one cycle time.
There are five CPU registers:
A is the 15-bit Program Counter register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is the 8-bit address register, can be auto incremented or
decremented.
X is the 8-bit alternate address register, can be lncremented
or decremented.
SP is the 8-bit stack pointer, points to subroutine stack (in
B, X and SP registers are mapped into the on chip RAM.
The B and X registers are used to address the on chip RAM.
The SP register is used to address the program counter
stack in RAM during subroutine calls and returns.
OZZLBdOOIOlZLQdOO/OOZABdOO
COP8720C/COP8721C/COP8722C
Functional Description (Continued)
MEMORY
The COP87200 contains 1 Kbyte of Program EEPROM, 64
bytes of on-chip RAM and Registers, I/O, 64 bytes of Data
EEPROM and 256 bytes of firmware ROM.
PROGRAM MEMORY
Program memory for the COP8720C consists of two mod-
ules--the 1 Kbyte program EEPROM and the 256 byte
ROM which contains the firmware routines for reading and
programming the EEPROM.
Memory locations in the 1 Kbyte program EEPROM module
are accessed by the address register, EEAR, and the data
register, EROMDR. The EEAR is mapped into the address
locations E2 and E3. The EFtOMDR register is located at
the address E1.
Under normal conditions, the program EEPROM and tho
ROM are addressed by the PC and their contents go to the
instruction bus. During the EEPROM program and verify cy-
cie, the EEPROM is treated as data memory while the
COP872OC is executing out of the firmware ROM. The
EEPROM is addressed through the EEAFl register. The
EROMDR register holds the data read back from the
EEPROM location during a verify cycle and holds the data
to be written into the EEPROM location during a program
cycle. The verify cycle takes 1 instruction cycle and the
write cycle takes 20 ms.
Accesses to the program EEPROM is controlled by two
flags, AEN and PEN, in the control register, EECR.
AEN PEN Access Type
0 0 Normal
0 1 Normal
1 0 EEPROM Read Cycle
1 1 EEPROM Write Cycle
To prevent accidental erasures and over-write situations the
application program should not set the AEN and PEN flags
in the EECR register. The COP87200 supports application
accesses to the EEPROM module via two subroutines in the
firmware ROM-an EEPROM read and an EEPROM write
subroutine. To program an EEPROM memory location, the
user loads the EECR and EROMDR registers and invokes
the write subroutine at the address 4000 Hex. To read an
EEPROM location the user loads the EEAR register with the
address of the EEPROM memory location and invokes the
mad subroutine at the address 4004 Hex. The read subrou-
tine returns the contents of the addressed EEPROM loca-
tion in the EROMDR register.
DATA MEMORY
The data memory for the COP87ZOC consists of on-chip
RAM, EEPROM, HO and registers. Data memory is ac-
cessed directly by the instruction or indirectly by the B, X
and SP registers.
The COP87200 has 64 bytes of RAM. Sixteen bytes of RAM
are mapped as "registers" that can be loaded efficiently,
decremented and tested. Three specific registers: B, X and
SP are mapped into this space. the other bytes are available
for general use.
The instruction set of the COP87200 permits any bit in the
data memory to be set, reset or tested. All I/O and the
registers (except tho A and PG) are memory mapped; there-
fore, l/O bits and register bits in addition to the normal data
RAM can be directly and individually set, reset and tested.
DATA EEPROM
The COP87200 provides 64 bytes of EEPROM for nonvola-
tile data memory. The data EEPROM can be read and pro-
grammed in exactly the same way as the RAM. All instruc-
tions that perform read and write operations on the RAM
work similarly upon the data EEPROM.
A data EEPROM programming cycle is initiated by an in-
struction such as X, LD, SBIT or RBIT. The EE memory
support circuitry sets the BsyERAM flag in the EECR regis-
ter immediately upon beginning a data EEPROM write cycle.
It will be automatically reset by the hardware at the end of
the data EEPROM write cycle. The application program
should test the BsyERAM flag before attempting a write op-
eration to the data EEPROM. A second EEPROM write op-
eration while a write operation is in progress will be ignored.
The Werr flag in the EECR register is set to indicate the
error status.
SIGNATURE AND OPTION REGISTERS
The COP87200 provides a set of six additional registers
implemented with EEPROM cells-the Signature and Op-
tion registers.
The Signature register is a tour-byte register provided for
storing ROM code rev. numbers or other application specific
information. The Signature register is shadowed behind the
data EEPROM cells at addresses BC to SF Hex. Two test
modes are provided to allow the Signature register to be
read or programmed.
The Option register consists of two bytes shadowed behind
the addresses 89 and BB Hex. The Option register allows
the COP8720C to be programmed to accurately emulate the
different mask options available on the COP820C.
ROMemu x 0 89 Hex
HS RC XTAL x " Hex
ROMemu: When set, the Data EEPROM and all the EE re-
lated registers become inaccessible. Thus, the EE registers
look like nonexistent memory locations when addressed by
the application program and the Program EEPROM be-
haves just like ordinary ROM. Thus, setting the ROMemu bit
allows the COP8720C to emulate the ROM based
COP820C with 100% accuracy.
HS, RC, XTAL: These three bits allow the COP8720C to
emulate the clock options of the COP8200. Note that only
five out of the possible eight combinations are Iegar--the
combinations 0E, oc and 06 are illegal combinations.
EECR and EE SUPPORT CIRCUITS
The EEPROM program and data modules share a common
set of EE support circuits to generate an necessary high
Functional Description (Continued)
m- I 20 -A11 Mt 1
tro-. 2 " -A10 ttTr- 2
Mt- 3 18 ~19 m:- ,
NC- 4 " -" 'te- t
CK- 5 " '-ttTs'tT CSP" 5
vcc- s 15 -tlNt1 YCC-I e
m- 7 " -ADT uc- 7
Am- 8 15 -AI)6 Ito-' a
'ln-- 9 12 -AD§ 'tlo- '
ADJ- " 11 -m m- 10
N)2- 11
TLIDDIQ105-1B ‘33- 12
24 -hlt RDY- 1 28 -htt
" C.'l0 ttTy-.. 2 27 "1°
22 '-A9 VR- 3 " -A3
21 -u NC- 4 " "5
20 l-RBET cto- ' " -ets0
" -tltio VCC- 6 " -GNO
" --te) NC- 7 " -NC
17 -" NC- 8 21 "-)IC
" -AD7 NC- , 20 .-tk
15 -ADG Nth- 10 " -NC
" .A05 'tht- 11 " h"A137
" C-Aiu hot- 12 " --hin
‘01.. 13 " -A05
TL/DD/9t08-10 AIU-t 14 15 PAM
TLIDD/9108-20
FIGURE 4. Plnouts for the COPBTZOC in Programming Mode
voltage programming pulses. Each programming cycte con-
sists of a 10 ms erase cycle followed by a 10 ms write cycle
for each byte. An EEPROM cell in the erase state is read
out as a 0 and the written state is read out as a 1. Since the
two EE modules share the support circuitry, programming
the two modules at the same time is not allowed.
The EECR register provides control, status and test mode
functions tor the EE modules.
The EECR register bit assignments are shown below.
EECR Register Bit Assignment
Wr Test Mode Codes AEN PEN
Rd Test Mode Codes BsyEROM BsyERAM AEN Werr
Bit 7 6 5 4 3 2 1 0
Werr Write Error. Writing to data EEPROM while a
previous write cycle is still busy, that is
BsyEFtAM is not o, causes Werr to be set to 1
indicate error status. Werr is cleared by writing
a 0 into it.
A program EEPROM programming cycle is
started by setting PEN and AEN to 1 at the
same time. PEN is "written thru". It is not
latched.
EECR bit 1 is read as the lock out indicator. A
low Vcc detector is enabied at the start of the
EE programming cycle. If it finds Vcc less than
VLKO- the Vue, status bit is set and the write
cycle is aborted. The VLKO status bit stays
latched until the start of another EE program-
ming cycle.
AEN controls the program EEPROM address/
data interface. when AEN is 0, the EEPROM is
the program memory. It is adressed by PC, and
its output data goes onto the instruction bus.
When AEN is set to 1, the EEPROM becomes
data memory. It is addressed by the EEAR, and
it is accessed from the EROMDR.
BsyERAM Set to 1 when data EEPROM is being written, is
automatically reset by the hardware upon com-
pletion of the write operation.
Set to 1 when program EEPROM is being writ-
ten, is automatically reset by the hardware
upon completion of the write operation.
Bits 3 to 7 of the EECFt are used for encoding various
EEPROM module test modes, most of which are for factory
manufacturing tests. Two of the test modes used for ac-
cessing the signature and option registers are described in a
previous section. The EE test modes are activated by apply-
ing high voltage to the RESET pin. Some of the test modes,
if activated improperly, can make the part inoperable. These
test modes are reserved for use by the manufacturer only.
The EECR register is cleared by RESET. EECR is mapped
into address location E0.
When either BsyERAM or BsyEROM is set to I, that is an
EEPROM programming cycle is in progress, the AEN bit is
locked up and cannot be changed by the processor.
EXTERNALLY PROGRAMMING THE PROGRAM
EEPROM
As shown in the previous section, the COP8720C permits
the program EEPROM memory module to be altered under
program control via the EECR register. To facilitate ease of
development the COP8720C also provides an external
mode of loading executable code into the program
EEPROM module.
This section describes the programming method for the
COP8720C EEPROM.
Programming the COP87200 EEPROM or the special regis-
ters is initiated by applying VPRG to the RESET pin. Control
gets transferred to the firmware ROM when VpRG is applied
to the RESET pin. The program contained in the firmware
ROM sets up the I/O of the COP8720C to simulate the 1/0
requirements of a 2-kbyte memory device. This is done by
setting up the COPB720C I/O as eight bits of address/data
lines, three address lines, read/write control and a ready
signal.
BsyEFtOM
OZZLRdOO/Ol3£8d00l003£8d00
COP87200/COP8721C/COP87226
Functional Description (Continued)
Figure 4 shows the three packages and the associated I/O.
The pin descriptions are as follows:
Vcc Positive 5V Power Supply
GND Ground
RE ET Active Low Reset Input
CKi Clock Input
ADO-AD7 Multiplexed Address/ Data Lines
A8-A11 Address Lines
AT5 Active Low Read Strobe
WR Active High Write Strobe
RDY Active High Ready Output
The firmware ROM program allows the user to reference
the special registers as EEPROM memory locations in the
address range 2048-2070 decimal. The following mapping
is used:
Signature Register fl at EEPROM address 800 Hex
Signature Register #2 at EEPROM address 801 Hex
Signature Register " at EEPROM address 802 Hex
Signature Register f4 at EEPROM address 803 Hex
Option Register #1 at EEPROM address 804 Hex
Option Register " at EEPROM address 805 Hex
Note that in order to reference these registers the user must
come in with addresses in the range 800 Hex to 805 Hex.
PROGRAMMING STEPS
The programmig host has to go through the following steps
for the write and verify cycles. (See Figure a
WRITE:
I. Powi is applied with the §ESET and WR pins low and
the RD high.
2. RESET is then brought up to Vprg within 1 ps.
3. The lower byte of the address to be written into is applied
to the pins ADO-AD? and the upper 3 bits of the address
applied to the pins A8-A11.
4. Observing the setup times, WR is brought high.
5. The data to be programmed is applied to the pins ADO-
6. The RDY signal from the COP87200 goes low. This ind.
cates that the WR and data on ADO-AD7 have been ac-
cepted and these inputs can be removed.
7. The programming host must now either wait for the RDY
signal to go high or wait at least 20 ms before initiating a
new programming cycle.
VERIFY:
1. Power is applied with R-EM-T and WR pins held low and
the E15 high.
2. The RE§ET pin is brought up to Vprg within 1 MS.
3. The lower byte of the address to be read is applied to the
pins ADO-AD7 and the upper three bits to the pins ADB-
4. Observing setup times the W pin is brought low.
5. After a time T7, the RDY signal from the COP87200 goes
low and data is ready for the host on the pins ADO-AD7.
The data Mays until the m signal goes back high after
which the RDY signal will go back high.
6. The host must wait for the RDY signal to go back high
before the next read cycle is initiated.
The 'err input when pulled low initializes the microcon-
troller. Initialization will occur whenever the REEET input is
pulled iow. Upon initialization, the ports L and G are placed
in the TRI-STATE mode and the Port D is set high. The PC,
PSW and CNTRL registers are cleared. The data and con-
figuration registers for Ports L 8. G are cleared.
The external RC network shown in Figure 5 should be used
to ensure that the RE§ET pin is held low until the power
supply to the chip stabilizes.
S REIT
t T. t nun
- I TL/Do/awa-o
RC 2 " Power Supply Rise Time
FIGURE 5. Recommended Reset Circuit
OSCILLATOR CIRCUITS
Figure 6 shows the three clock oscillator configurations
available for the COP87200.
A. CRYSTAL OSCILLATOR
The COP87ZOC can be driven by a crystal clock. The crystal
network is connected between the pins CKI and CKO.
Table t shows the component values required for various
standard crystal values.
B. EXTERNAL OSCILLATOR
CKI can be driven by an external clock signal. CKO is avail-
able as a general purpose input and/or HALT restart con-
c. n/c OSCILLATOR
CKI is configured as a single pin RC controlled Schmitt trig-
ger oscillator. CKO is available as a general purpose input
and/or HALT restart control.
Table II shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
Itlu Mtttl - cm "ttl
m EXTERKAL
- - CKI cm
- TL/DD/9108-10
FIGURE 6. Crystal and RAt Cttnntttttltttt Diagrams
OSCILLATOR OPTIONS
The COP8720C can be driven by clock inputs between DC
and 20 MHz. For low input clock frequencies is: 5 MHz) the
instruction cycle frequency can be selected to be the input
clock frequency divided by 10. This mode is known as the
Normal Mode.
Functional Description (Continued)
TABLE I. Crystal Osclllator Configuration, TA = 25°C
R1 R2 Ct C2 CKI Freq
Conditions
(k0) (Mm (PF) (PF) (MHz)
0 1 30 30-36 20 VCC = 5V
0 1 30 30-36 10 VCC = 5V
0 1 30 30-36 4 (:- 20) VCC = 2.5V
0 1 200 100-150 0.455 Vcc = 2.5V
TABLE II. RC Oscillator Conf1guratlort, TA --- 25'C
R C CKI Freq. Instr. Cycle
Condltlons
(kn) (PF) (MHz) (ps)
3.3 82 2.8-2.2 3.6-4.5 Vcc = 5V
5.6 100 1.5-1.1 6.7-9 Voc = 5V
6.8 100 IA-0.8 9-12.5 Vcc == 2.5V
For oscillator frequencies that ate greater than 5 MHz the
chip must run with a divide by 20. This is known as the High
Speed mode.
The COP82OC microcontroller has thm mask options for
configuring the clock input. To emulate these mask options
3 bits must be set in the Option register.
HS ac XTAL Mask Optlon
1 0 1 High Speed Crystal
0 0 1 Normal Mode Crystal
1 0 0 High Speed External
0 O 0 Normal Mode External
0 1 0 RIC Oscillator
The CKI and CKO pins are automatically configured upon
selecting a particular option.
- High Speed Crystal (CKI/20) CKO for crystal configure
- Normal Mode Crystal (CKI/10) CKO for crystal configu-
ration
- High Speed External (CKI/20) CKO available as G7 in-
- Normal Mode External (CKl/ 10) CKO available as G?
- R/C (CKI/10) CKO available as Gr input
Where, G7 can be used either as a general purpose input or
as a control input to continue from the HALT mode.
CURRENT DRAIN
The total current drain of the chip depends on:
1) Oscillator operating mode-ll
2) Internal switching tgutrtmt---i2
3) Internal leakage current-lt?
4) Output source current-l4
5) DC current caused by external input not at Vcc or GND-
Thus the total current drain, It is given as
It=l1+l2+13+l4+l5
To reduce the total current drain, each of the above compo-
nents must be minimum.
The chip will draw the least current when in the normal
mode. The high speed mode will draw additional current.
The R/C mode will draw the most. Operating with a crystal
network will draw more current than an external square-
wave. Switching current, governed by the equation below,
can be reduced by lowering voltage and frequency. Leak-
age current can be reduced by lowering voltage and tem-
perature. The other two items can be reduced by carefully
designing the end-user's system.
lit = C x V x f
C = equivalent capacitance of the chip. (T BD)
V = operating voltage
f = CKI frequency
The typical capacitance for the COPBZOC is TBD pF.
Some sample current drain values at Vcc = 6V are:
CKI (MHz) Inst. Cycle but) It (mA)
20 1 13
3.58 3 2.2
2 5 1.2
0.3 33 0.2
0 (HALT) - <0.01
HALT MODE
The COP87ZOC supports a power saving mode of opera-
tion: HALT. The controller is placed in the HALT mode by
setting the G7 data bit, alternatively the user can stop the
clock input. In the HALT mode all internal processor activi-
ties including the clock oscillator are stopped. The fully stat-
ic architecture freezes the state of the controller and retains
all information until continuing. In the HALT mode. power
requirements are minimal as it draws only leakage currents
and output current. The applied voltage (Vcc) may be de-
creased down to W (minimum RAM retention voltage) with-
out altering the state of the machine.
There are two ways to exit the HALT mode: via the RESET
or by the CKO pin. A low on the RESET tine reinitializes the
OZZLBdOO/OI-ZLBdOO/OOZleOO
COP8720C/COP8721C/COP8722C
Functional Description (Continued)
microcontroiier and starts executing from the address
OOOOH. A low to high transition on the CKO pin causes the
microcontroller to continue with no reinitialization from the
address following the HALT instruction. This also resets the
G7 data bit.
INTERRUPTS
The COP87200 has a sophisticated interrupt structure to
allow easy interface to the real world. There are three possi-
ble interrupt sources, as shown below.
A maskable interrupt on external GO input (positive or nega-
tive edge sensitive under software control).
A maskeble interrupt on timer carry or timer capture.
A non-maskable sottware/error interrupt on opcode zero.
INTERRUPT CONTROL
The GIE (global interrupt enable) bit enables the interrupt
function. This is used in conjunction with ENI and ENTI to
select one or both of the interrupt sources. This bit is reset
when interrupt is acknowledged.
ENI and ENTI bits select external and timer interrupt re-
spectively. Thus the user can select either or both sources
to interrupt the microcontroller when GIE is enabled.
IEDG selects the external interrupt edge. (0 = rising edge.
1 == tailing edge). The user can get an interrupt on both
rising and falling edges by toggling the state of IEDG bit
after each interrupt.
IPND and TPND bits signal which interrupt is pending. After
interrupt is acknowledged, the user can check these two
bits to determine which interrupt is pending. This permits the
interrupts to be prioritized under software. The pending flags
have to be cleared by the user. Setting the GIE bit high
inside the interrupt subroutine allows nested interrupts.
The software interrupt does not reset the GIE bit. This
means that the controller can be interrupted by other inter-
rupt sources while servicing the software interrupt.
INTERRUPT PROCESSING
The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice. The Global Interrupt Enable (GlE) bit is
reset to disable further interrupts. The microcontroller then
vectors to the address OOFFH and resumes execution from
that address. This process takes 7 cycles to complete. At
the end of the interrupt subroutine, any of the following
three instructions return the processor back to the main pro-
gram: RET, RETSK or RETI. Either one of the three instruc-
tions wilt pop the stack into the program counter (PC). The
stack pointer is then incremented twice. The RETI instruc-
tion additionally sets the GIE bit to re-enable further inter-
rupts.
Any of the three instructions can be used to return from a
hardware interrupt subroutine. The RETSK instruction
should be used when returning from a software interrupt
subroutine to avoid entering an infinite loop.
DETECTION OF ILLEGAL CONDITIONS
The COP8720C incorporates a hardware mechanism that
allows it to detect illegal conditions which may occur from
coding errors. noise and 'brown out' voltage drop situations.
Specifically it detects cases of executing out of undefined
ROM area and unbalanced stack situations.
Reading an undefined ROM location returns 00 (hexadeci-
mal) as its contents. The opcode for a software interrupt is
also 'OO'. Thus a program accessing undefined ROM will
cause a software interrupt.
Reading an undefined RAM location returns an FF (hexade-
cimal). The subroutine stack on the COP87200 grows down
for each subroutine call. By initializing the stack pointer to
the top of RAM, the first unbalanced return instruction will
cause the stack pointer to address undefined RAM. As a
result the program will attempt to execute from FFFF (htaxa-
decimal), which is an undtyfintyd ROM location and will trig-
ger a software interrupt.
MlCROWlRE/PLUSTM
MICROWIRE/PLUS is a serial synchronous bidirectional
communications interface. The MlCROWIFlE/PLUS capabil-
ity enables the COP87200 to interface with any of National
Semiconductor‘s Microwire peripherals (i.e. A/ D converters,
display drivers, etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of an 8-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure 8 shows
the block diagram of the MICROWIRE/PLUS interface.
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWlREf
PLUS arrangement with the internal clock source is called
the Master mode of operation. Similarly, operating the
MlCROWIFtE/PLUS arrangement with an extemai shift
clock is called the Slave mode of operation.
The CNTRL register is used to configure and control the
MlCROWiRE/PLUS mode. To use the McROWlRE/PLUS,
the MSEL bit in the CNTRL register is set to one. The SK
clock rate is selected by the two bits, SO and SI, in the
CNTRL register. Table III details the different clock rates
that may be selected. T
TABLE III
St so SK Cycle Time
0 0 mo
0 1 Mg
1 x Etc
where,
to is the instruction cycle clock.
[em] tz? GE
:mmw. _ -
mm tl- Init) l
TIMER _ - to
TPND _ INTERRUPT
uumnow D-- LOGIC
SOFTWARE
TL/DD/91OB-11
FIGURE 7. Interrupt Block Diagram
Functional Description (Continued)
MlCFlOWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the
MlCROWlRE/PLUS arrangement to start shifting the data.
It gets reset when eight data bits have been shifted. The
user may reset the BUSY bit by software to allow less than
8 bits to shift. The COP8720C may enter the MICROWIRE/
PLUS mode either as a Master or as a Slave. Figure 9
shows how two COP87200 microcontrollers and several pe-
ripherals may be interconnected using the MlCFlOWIRE/
PLUS arrangement.
Master MlCROWIRE/PLUS Operation
in the MlCROWlFlE/PLUS Master mode of operation the
shift clock (SK) is generated internally by the COP8720C.
The MlCROWlRE/PLUS Master always initiates all data ex-
changes. (See Figure g.) The MSEL bit in the CNTRL regis-
ter must be set to enable the SO and SK functions onto the
G Port. The so and SK pins must also be selected as out-
puts by setting appropriate bits in the Port G configuration
register. Table N summaries the bit settings required for
Master mode of operation.
SLAVE MICROWIREIPLUS OPERATION
in the MICRtyMRE/PLUS Slave mode of operation the SK
clock is generated by an external source, Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by appropriately
setting up the Port G configuration register. Table IV sum-
marizes the settings required to enter the Slave mode of
operation.
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated. (See Figure 9.)
8 - BIT so ' SI
D REGISTER
T SHIFT CLOCK
B CLOCK
S k - SELECT SK
TL/DD/tMOB-ll?
FIGURE tk MlCROWIRE/PLUS Btock Dlagram
TABLEIV
' as IM as G8
Cottttg.Contig. Fun Fun. Fun Operation
Bil Bit . .
1 1 so lnt.SK SI MlCROWlRE/PLUSMast
o 1 TFtl-STATE lnt.SK SI MICROWIREIPLUS Master
1 0 so Ext.SK SI MICROWIRE/PLUS Slave
0 o TRISTATE Ext.SK SI MlCROWIRE/PLUS Sieve
TIMER/COUNTER
The COP8720C has a powerful 16-bit timer with an associ-
ated 16-bit register enabling them to perform extensive tim-
er functions. The timer T1 and its register RI are each orga-
nized as two 8-bit read/write registers. Control bits in the
register CNTRL allow the timer to be started and stopped
under software control. The timer-register pair can be oper-
ated in one of three possible modes. Table V details various
timer operating modes and their requisite control settings.
MODE I. TIMER WITH AUTO-LOAD REGISTER
In this mode of operation the timer T1 counts down at the
instruction cycle rate. Upon undertlow the value in the regis-
ter RI gets automatically reloaded into the timer which con-
tinues to count down. The timer underflow can be pro-
grammed to interrupt the microcontroller. A bit in the control
register CNTRL enables the TlO (G3) pin to toggle upon
timer tmdttrtlDwtt. This allow the generation of square-wave
outputs or pulse width modulated outputs under software
control. (See Figure 10.)
MODE 2. EXTERNAL COUNTER
In this mode. the timer T1 becomes a 16-bit external event
counter. The counter counts down upon an edge on the TIO
pin. Control bits in the register CNTFtL program the counter
to decrement either on a positive edge or on a negative
edge. Upon underflow the contents of the register R1 are
automatically copied into the counter. The underflow can
also be programmed to generate an interrupt. (See Figure
MODE 3. TIMER WITH CAPTURE REGISTER
Timer T1 can be used to precisely measure extemai fre-
quencies or events in this mode of operation. The timer T1
counts down at the instruction cycle rate. Upon the occur-
rence ot a specified edge on the TIO pin the contents of the
timer T1 are copied into the register R1. Bits in the control
register CNTFtL allow the trigger edge to be specified either
as a positive edge or as a negative edge. In this mode the
user can elect to be interrupted on the specified trigger
edge. (See Figure th)
OZZLBdOOIOlZLOdOO/OOZLBdOO
COP87200/COP8721C/COP8722C
Functional Descrlption (Continued)
CHIP SELECT LINES ,5
cs ds cs cs cs
I/O LOW I/O
L0IES 3-911 102 " an POWER mm. LCD LINES
comm A/D CON - :mou cuos GEN. & DISPLAY comm
(MASTER) vzm cams m COUNTER DRNER (SLAVE)
00P43X & TIMER COP452L COP”!
DO DI CLK oo DI CLK 00 th CLK DO th CLK DI cut
l A A l A A l d n A l A A A A
SI A SO
so D SI
Stt SK
TLIDD/D108-13
FIGURE 9. MlCR0WlREff'LUS Applltttttlon
TABLE V. Tlmor Oporatlng Modal
CNTRL Tlmor
Bite Oporatlon Mode T Interrupt Counts
7 6 5 On
0 0 0 External Counter W/Auto-Load Reg. Timer Carry TIO Pos. Edge
0 o 1 External Counter W/Auto-Load Reg. Timer Carry T10 Neg. Edge
0 1 0 Not Allowed Not Allowed Not Allowed
01 1 NotAllowed Not Allowed Not Allowed
1 0 0 Timer W/Auto-Load Reg. Timer Carry to
1 0 1 Timer WIAuto-Load Reg./Togg1e T10 Out Timer Carry to
1 1 0 Timer W/Capture Register TIO Pos. Edge tc
1 1 1 Timer W/Capture Register TIO Neg. Edge ttt
I INTERNAL DATA BUS I l INTRNAL DATA BUS ,
TIMER INTERRUPT
UNDERFLOW
" - " AUTO 'NTERRUPT RI
RELCMD REG. m--l iill- t 16 - BIT
f ' CAPTURE REG.
1s - arr nun]
COUNTER
63 mm no
LATCH *oumn
TL/ DD/91 08- 15
FIGURE 10. Tlmer/Counter Auto
Reload Mode Block Diagram
16- BIT TIMER
TLIDD/B1OB-14
FIGURE 11. "mar Capture Mode Block Diagram
Functional Description (Continued)
TIMER PWM APPLICATION
Figure 12 shows how a minimal component D/A converter
can be built out of the Timer-Register pair in the Auto-Re-
load mode. The timer is placed in the "Timer with auto re-
loa " mode and the TIO pin is selected as the timer output.
At the outset the TIO pin is set high, the timer T1 holds the
on time and the register R1 holds the signal off time. Setting
TRUN bit starts the timer which counts down at the Instruc-
tion cycle rate. The undertlow toggles the TIO output and
copies the off time into the timer, which continues to run. By
alternately loading in the on time and the oft time at each
successive interrupt a PWM frequency can be easily gener-
c /;fflx\
o A SIMPLE o- -A
P "i'vvtg..11 comm usmc
3 THE mm T0
1 T GENERATE A PIN
2 OUTPUT.
TLfDDnrt06-t6
FIGURE 12. Timer Application
Control Registers
CNTRL REGISTER (ADDRESS X'OOEE)
The Timer and MtCROWiRE/PLUS control register contains
the following bits:
SI & so Select the MICROWIRE/PLUS stock divide-by
IEDG External interrupt edge polarity select
(0 == rising edge, 1 == falling edge)
MSEL Enable MlCROWIFtE/PLUS functions SO and SK
TRUN Start/Stop the Timer/Counter (1 = run, o ==
T03 Timer input edge polarity select (0 = rising edge,
== falling edge)
TC2 Selects the capture mode
TCI Selects the timer mode
TRUNIMSELI IEDG S1 so
TC1 I TC2 I me
PSW REGISTER (ADDRESS x’OOEF)
The PSW register contains the following select bits:
GIE Global interrupt enable
ENI External interrupt enable
BUSY MICROWIRE/PLUS busy shifting
IPND External Interrupt pending
ENTI Timer interrupt enable
TPND Timer interrupt pending
C Carry Flag
HC Half carry Flag
I HC C ITPND I ENTI I IPND BUSY I ENI GIE
Bit7 BitO
Operating Modes
These controllers have two operating modes: Single Chip
mode and the ROMless mode. The operating mode is deter-
mined by the state of the D2 pin at power on reset.
SINGLE CHIP MODE
In the Slngle Chip mode, the controller functions as a salt
contained microcontroller. It can address internal RAM and
ROM. All ports configured as memory mapped l/O ports.
ROMLESS MODE
The COP872OC will enter the ROMless mode of operation if
the D2 pin is held at logical "ty' at reset. In this case the
internal PROGRAM EEPROM is disabled and the controller
can now address up to 32 Kbytes of external program mem-
ory. It continues to use the on board RAM, and DATA
EEPROM.
Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Address Contents
00 to 2F On Chip RAM Bytes
30 to 7F Unused RAM Address Space (Reads as all Ones)
80 to BF 64 Bytes DATA EEPROM
co to CF Expansion Space for I/O and Registers
Do to DF On Chip I/O and Registers
DO Port L Data Register
DI Port L Configuration Register
D2 Port L Input Pins (Read Only)
D3 Reserved for Port L
D4 Port G Data Register
D5 Port G Configuration Register
D6 Port G Input Pins (Read Only)
D7 Port I Input Pins (Read Only)
DS-DB Reserved for Port C
DC Port D Data Register
DD-DF Reserved for Port D
EO to EF On Chip Functions and Registers
E0 EECFt
E1 EROMDR
E2 EEAR Low Byte
E3 EEAR High Byte
E4-E8 Reserved
E9 MlCROWlRE/PLUS Shift Register
EA Timer Lower Byte
EB Timer Upper Byte
EC Timer Autoload Register Lower Byte
ED Timer Autoload Register Upper Byte
EE CNTRL Control Register
EF PSW Register
F0 to FF On Chip RAM Mapped as Registers
FC X Register
FD SP Register
FE B Register
OZZLSdOO/OlZLBdOO/OouadOO
COP8720C/COP8721C/COP872ZC
Memory Map (Continued)
Reading unused memory locations below TFH will return all
ones. Reading other unused memory locations will return
undefined data.
Addressing Modes
REGISTER INDIRECT
This is the "norma " mode of addressing for the COP8720C.
The operand is the memory addressed by the B register or
X register.
DIRECT
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
IMMEDIATE
The instruction contains an 8-bit immediate field as the AF
erand.
REGISTER INDIRECT
(AUTO INCREMENT AND DECREMENT)
This is a register indirect mode that automatically incre-
ments or decrements the B or X register aftet executing the
instruction.
RELATIVE
This mode is used for the JP instruction, the instruction field
is added to the program counter to get the new program
location. JP has a range of from -31 to + 32 to allow a one
byte relative jump (JP + 1 is implemented by a NOP instruc-
tion). There are no 'pagas' when using JP, all 15 bits of PC
are used.
Instruction Set
REGISTER AND SYMBOL DEFINITIONS
Registers
A 8-bit Accumulator register
B 8-bit Address register
X 8-bit Address register
SP 8-bit Stack pointer register
PC 15-bit Program counter register
PU upper 7 bits of PC
Pl. lower 8 bits of PC
C 1-bit of PSW register for carry
HC Half Carry
GIE 1-bit of PSW register for global interrupt enable
Symbols
M Memory indirectly addressed by B register
MI Memory indirectly addressed by X register
Mem Direct address memory or IBI
Meml Direct address memory or M or Immediate data
lmm 8-bit Immediate data
Reg Register memory: addresses F0 to FF (Includes B, X
and SP)
Bit Bit number (0 to 7)
- Loaded with
_ Exchanged with
Instruction Set (Continued)
Instruction Set
ADD add A - A + Meml
ADC add with carry A (- A + Meml + 0.0 - Carry
HC - HalfCarry
SUBC subtract with carry A q-- A + Hem! +C, C - Carry
HC - HaifCany
AND Logical AND A - A and Meml
OR Logical OR A - A or Marni
XOR Logical Exclusive-OR A - Axor Mernl
IFEQ IF equal Compare A and Meml, Do next if A == Meml
IFGT IF greater than CompareA and Meml, Do next if A > Meml
IFBNE IF B not equal Do next if lower 4 bits of B = lmm
DRSZ Decrement Reg. .skip it zero Reg - Reg - l, skip if Reg goes to 0
SBIT Set bit 1 to bit,
Mem (bit= 0 to 7 immediate)
RBIT Reset bit 0 to bit,
IFBIT if bit If hit,
Mem is true, do next Instr.
X Exchange A with memory A H Mem
LD A Load A with memory A q-- Meml
LD mam Load Direct memory immed. Mern - lmm
LD Reg Load Register memory immed. Reg - Imm
X Exchange A with memory [B] A - [B] (B - B KI)
x EytchangttAwith memory MI A H M (X - Xtll
LDA LoadAwith memorle] A - [B] (B - th1)
LD A Load Awith memory M A - MI (X - Xt 1)
LDM Load Memorylmmediate [B] - lmm (B - Bt1)
CLRA ClearA A - 0
INCA incrementA A - A + 1
DECA DecrementA A - A - 1
LAID Load A indirect from ROM A - ROM(PU,A)
DCORA DECIMAL CORRECT A A - BCD correction (follows ADC, SUBC)
RRCA ROTATEARIGHTTHRUC C - A7 - ... - A0 - C
SWAPA Swap nibbles ofA A7 . . . A4 - M _ . .Ao
SC SMC C_-1,HCe-- 1
RC ResetC C - o, HC - 0
IFC If C If C is true. do next instruction
IFNC If not C If C is not true, do next instruction
JMPL Jump absolute long PC - " = 15 bits,0 to 32k)
JMP Jump absolute PCi1..0 - it's = 12 bits)
JP Jump relative short PC q- PC + " is -3I to +32, not 1)
JSRL Jump subroutinelong [SP] - PL,[SP-1l - PU.SP-2.PC - ii
JSR Jump subroutine [SP] - PL.[SP-1l q- PU.SP-2.PC11..0 - I
JID Jumpindirect PL - ROM(PU,A)
RET Return from subroutine SP+2,PL - [SP].PU - isp-tl
RETSK Returnand Skip SP+2,PL - [SPLPU - [SP-1],Skip nexnnstrucuon
RETI Return from Interrupt SP+2,PL - [SP],PU - [SP-1].GIE - 1
INTR Generate an interrupt [SP] - PIP-tl - PU,SP-2,PC - OFF
NOP No operation PC - PC + 1
OZZLBdOO/OLZLBdOOIOOZLBdOO
COP87200/COP8721CICOP87226
Blts 7-4
JP -15
JP -31
LB 0F0,#i
DRSZ OFO
ADC A,
ADC A.
0. [B]
LD B, 0F
IFBNE 0
OOOO-OOFF
OOOO-OOFF
JP -14
JP -30
LDOF1,#i
DRSZ 0F1
SUBC A.
A! [B]
LD B, 0E
IFBNE 1
0100-01FF
0100-01 FF
JP —13
JP -29
LB 0F2,#i
DRSZ OFZ
IFEQ A,
LD B, CD
IFBNE 2
0200-02FF
0200-02FF
JP -12
JP -28
L0 0F3, #i
DRSZ 0F3
IFGT A.
A. [B]
LD B, 00
IFBNE 3
0300-03FF
0300-03FF
JP -11
JP -27
L0 0F4. #i
DHSZ 0F4
ADD A,
LDB,OB
IFBNE 4
O400-04FF
0400-04FF
JP -10
JP —26
L0 0F5,#i
DHSZ 0F5
AND A,
LD 8, 0A
IFBNE 5
OSOO-OSFF
0500-05FF
JP -25
L0 0F6, #i
DRSZ 0F6
XOR A.
L0 8.9
IFBNE 6
0600-06FF
0600-06FF
JP -24
L0 0F7,#i
DRSZ OF7
7. [Bl
L0 5.8
IFBNE 7
0700-07FF
0700-07FF
JP -23
L0 0F8, #l
DRSZ 0F8
0. [B]
LD 8,7
IFBNE 8
OBOO-OBFF
0800—08FF
JP -22
LB 0F9, #i
DRSZ 0F9
L0 8.6
IFBNE 9
0900-09FF
0900-09FF
JP -21
L0 OFA, #i
DRSZ OFA
[B+l.#i
LD 8, 5
IFBNE 0A
OAOO-OAFF
OAOO-OAFF
JP -20
L0 OFB, #i
DRSZ OFB
L0 8.4
IFBNE OB
OBOO-OBFF
OBOO-OBFF
JP -19
L0 OFC. #i
DRSZ OFC
LD Md.
X A,Md
L0 3.3
IFBNE OC
OCOO-OCFF
OCOO-OCFF
JP -18
LD OFD, #i
DRSZ OFD
L0 8.2
IFBNE OD
ODOO-ODFF
ODOO-ODFF
LD OFE. #i
DHSZ OFE
[B]. #i
6, [B]
6. [B]
L0 8.1
IFBNE OE
OEOO-OEFF
OEOO—OEFF
LD 0FF,#1
DRSZ OFF
L0 8.0
IFBNE 0F
OFOO-OFFF
OFOO-OFFF
where.
i is the immediate dam
Md is a direcfly addressed memory location
‘ is an unused opooda (sea lollowing table)
OPCODE LIST
Bits 3-0
Irttgtrutttlttn Execution Tlme Bytes and Cycles per
Most instrutttiontt are single byte (with immediate address. Instruction
ing mode intttruetion taking two bytes). The following table shows the number of bytes and cycles
Most slngle instmctions take one cyele time (1 11-9 at for each instruction in the format of byte/cycle (a cycte is
20 MHz) to execute. 1 ”3 at 20 MHz).
See the BYTES and CYCLES per INSTRUCTION table for
details.
© Dlroct Immod.
ADD 1/1 3/4 2/2
ADC 1/1 3/4 2/2
SUBC 1/1 3/4 2/2
AND 1/1 3/4 2/ 2
OR 1/ 1 3/4 2/ 2
XOR 1/1 3/4 2/ 2
IFEQ 1/1 3/4 2/2
IFGT 1/1 3/4 2/2
IFBNE 1/1
DRSZ 1/3
SBIT 1/1 3/4
RBIT 1/1 3/4
IFBIT 1/1 3/4
Memory Transfer Instructions
Floglstor Roglstor Indirect
Indlroct Dlroct Immad. Autolncr & Docr
[B] MI [B+.B-l [x+.X-l
XA,' 1/1 1/3 2/3 1/2 1/3
LD A,' 1/1 1/3 2/3 2/2 1/2 1/3
LD B,imm 1/1 (If B < 16)
LD B/mm 2/3 (If B > 15)
LD Memem 2/2 3/3 2/2
LD Rngmm 2/3
. - > Memory location addressed by B or X or directly.
lnutructlom Uslng A a e Transfer of Control Instructions
CLRA 1/1 JMPL 3/4
INCA 1/1 JMP 2/3
DECA 1/1 JP 1/3
LAID 1/3 JSRL 3/5
DCORA 1/1 JSR 2/5
RRCA 1/1 JID 1/3
SWAPA 1/ 1 RET 1/5
SC 1/1 RETSK 1/5
RC 1/1 RETI 1 / 5
" 1/1 INTR 1/7
IFNC 1/1 NOP 1/1
OZZLBdOO/OlZleOO/OOZLBdOO
COP872OC/COP8721C/COP87220
Bytes and Cyles per
Instruction (Continued)
The following table shows the instructions assigned to un-
used opcodes. This table is for information only. The opefa-
tions performed are subject to change without notice. Do
not use these opcodes.
Unused Unused
Opcode Instruction o . Irtetrutttittrt
60 NOP A9 NOP
e1 NOP AF LD A, [Bi
62 NOP Bt C - HC
63 NOP B4 NOP
67 NOP es NOP
ac RET B? x A, M
99 NOP ee NOP
9F LD M, #i BF LD A, ix)
A7 x A, ©
A8 NOP
Development Support
MOLE DEVELOPMENT SYSTEM
The MOLE (Microcomputer On Line Emulator) is a low cost
development system and emuiator for all microcontroller
products. These include COPs. and the HPC family of prod-
ucts. The MOLE consists of a BRAIN Board, Personality
Board and optional host software.
The purpose ot the MOLE is to provide the user with a tool
to write and assemble code, emulate code for the target
microcontroller and assist in both software and hardware
debugging of the system.
It is a self contained computer with its own firmware which
provides for all system operation, emulation control, com-
munication. PROM programming and diagnostic operations.
To program the COP8720C, a special adapter board is pro-
vided. This adapter board contains a socket for the
COP8720C and plugs directly into the MOLE prom program-
It contains three serial ports to optionally connect to a termi-
nal, a host system, a printer or a modem, or to connect to
other MOLEs In a multi-MOLE environment.
MOLE can be used in either a stand alone mode or in con-
iunction with a selected host system using PC-DOS commu-
nicating via a RS-232 port.
How to Order
To order a complete development package, select the two.
tlon for the microcontroller to be developed and order the
parts listed.
Development Tools Selection Tebto
Order Manual
Mlttrttettntrttller Part Number Description Includes Number
MOLE-BRAIN Brain Board Brain Board Users Manual 420408188-001
MOLE.cOP8-PB1 Personality Board COP820/840 Personality Board
COP820/ Users Manual 420410806-001
COP840 MOLE-COPe-IBM Assembler Software for IBM copeoo Software Users Manual
. 424410527-001
and Software Disk
PC-DOS Communications
Software Users Manual 420040416-001
420410703-001 Programmer's Manual 420410703-001
Development Support (Continued)
DlAL-A-HELPER
Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Bulle-
tin Board Information System and additionally, provides the
capability of remotely accessing the MOLE development
system at a customer siie.
INFORMATION SYSTEM
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be ae..
cessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) tor communications to and from the Micro-
controller Applications Group and a FILE SECTION which
consists ot several file areas where valuable application
software and utilities could be found. The minimum require-
ment for accessing the Dial-A-Her is a Hayes Compatible
modem.
If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk1or
later use.
ORDER PIN: MOLE-DIAL-A-HLP
Information System Package Contains:
Dial-A-Helper User's Manual Pin
Public Domain Communications Software
FACTORY APPLICATIONS SUPPORT
Dial-A-Helper also provides immediate factory applications
support. If a user is having difficulty in operating a MOLE, he
can leave messages on our electronic bulletin board, which
we will respond to, or under extraordinary circumstances he
can arrange for us to actually take control of hls system via
modem for debugging purposes.
Voice. (408) 721 -5582
Modem: (408) 739-1 162
Baud: 300 or 1200 Baud
Setup: Length: B-Bit
Parity: None
Stop Bit 1
Operation: 24 Hours, , Days
DlAL-A-HELPER
.mi.q..t.-""ire.m.-a.-.."'.".e."--'"q...--q .---.--------------------.
I I I I
I I I I
I USER'S I I
I men I I I
t SYSTEM I I I
t I I I
t ' I I
. . HOST
I uoocu o g: I “WE” coupon]: I
I I I I
I I I I
I I I t
I I I I
' HOST ' '
I Bod comm I I I
I I I t
I I I I
I I I I
USER SITE
NATIONAL SEMICONDUCTOR SITE
TL/DD/ttlot)-"
OZZLBdOO/OlZleOO/OOZLBCIOO
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
COP8722CN - product/cop8722cn?HQS=T|-nu|I-null-dscatalog-df-pf-null-wwe
COP8721CN - product/cop8721cn?HQS=T|-nu|I-null-dscatalog-df—pf-nuII-wwe
COP8720CV - product/cop87200v?HQS=T|-nu|I-nulI—dscatalog-df-pf-nulI-wwe
COP8720CN - product/cop8720cn?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
