CLC5526MSAX ,Digital Variable Gain Amplifier (DVGA)CLC-DRCS7-PCASMDRCS7 Evaluation Board User’s GuideJanuary 2001CLC-DRCS7-PCASMDRCS7 Evaluation Board ..
CLC5602IM ,Dual/ High Output/ Video AmplifierElectrical Characteristics v f L s cm EE s L cmPARAMETERS CONDITIONS TYP MIN/MAX RATINGS UNITS NOTE ..
CLC5602IN ,Dual/ High Output/ Video AmplifierFeaturesThe National CLC5602 has a new output stage that delivers high ■130mA output currentoutput ..
CLC5612IM ,Dual/ High Output/ Programmable Gain BufferElectrical Characteristics v L s cm EE s L cmPARAMETERS CONDITIONS TYP MIN/MAX RATINGS UNITS NOTESA ..
CLC5612IN ,Dual/ High Output/ Programmable Gain Bufferapplications.8It also drives low impedance loads with minimum distortion.V = – 5VCC7The CLC5612 wil ..
CLC561AI ,Wideband, Low Distortion DriveR-AmpsFeatures■150MHz bandwidth at +24dBm output ■Low distortion (2nd/3rd:-59/-62dBc @ 20MHz and 10dBm)■ ..
CLC5526MSA.-CLC5526MSAX-CLC5902VLA
Digital Variable Gain Amplifier (DVGA)
CLC-DRCS7-PCASM
DRCS7 Evaluation Board User
January 2001
CLC-DRCS7-PCASM
DRCS7 Evaluation Board User’ s Guide
OverviewThe Diversity Receiver Chipset (DRCS) is an IF sampling receiver
optimized for GSM/EDGE systems. It provides the extreme
dynamic range required for EDGE through a novel AGC-based
architecture. The chipset consists of two CLC5526 Digital V ariable
Gain Amplifiers (DVGAs), two CLC5957 Analog-to-Digital Con-
verters (ADCs), and one CLC5902 Dual Digital Tuner/AGC.
The DRCS7 Evaluation Board (CLC-DRCS7-PCASM) supports
complete evaluation of the Diversity Receiver Chipset (DRCS).
Configuration of the Digital Tuner/AGC is controlled by a COP8
micro-controller. Several useful configurations can be directly
loaded by the COP8 or specialized configurations can be created
and loaded with the provided DRCS Control Panel software (drc-
scp.exe).
A Data Capture Board (CLC-CAPT-PCASM) and accompanying
software (capture.exe) are available for use with the DRCS7 Evalu-
ation Board. The Capture Board enables the user to capture and
transfer data from the DRCS7 Evaluation Board into a file on a PC.
Matlab® script files are provided to assist in data analysis.
Figure 1 shows a functional block diagram of the DRCS. The
DVGA controls the ADC’s input level to expand the dynamic
range. The ADC sub-samples the input and feeds the digitized IF to
the CLC5902. The CLC5902 mixes the IF with a digital oscillator,
removes the DVGA gain steps, and filters the result. A final output
of quadrature baseband signals is provided in both serial and paral-
lel formats.
IF Input
Input Clock
DVGAS 2FS …++
Filter to remove
broadband DVGA
noise at sampling
intervals. 150MHz
is the default tuning
frequency.
The undersampling
process looks like
mixing with multiples
of the input clock.
NCO
SINE COSINE
‘Q’
‘I’
Power
Detector
Channel
Filter
AGC
Compensation
AGC
Compensation
Channel
Filter
Integrator &
Control Table
AGC
Complex
Output
CLC5902 (one channel of two)CLC5957
CLC5526
Required Evaluation Items DRCS7 Board
(CLC-DRCS7-PCASM) +5V/1A power supply Signal generator DRCS Control Panel software PC running Windows® 95/98/NT Matlab® software or other data
analysis software One PC serial port
Suggested Evaluation Items Data Capture Board
(CLC-CAPT-PCASM) Data Capture Board software Second PC serial port
Reference Documents CLC5957 data sheet CLC5526 data sheet CLC5902 data sheet Data Capture Board User’s Guide Evaluation Board Interoperability
User’s Guide
