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CLC016
Data Retiming PLL With Automatic Rate Selection
Comlinear CLC016
Data Retiming PLL with Automatic Rate Selection
Applications SMPTE 259M serial digital interfaces: NTSC/PAL,
4:2:2 component, 360Mbps wide screen Serial digital video routing and distribution Clock and data recovery for high-speed data transmission Re-synchronization of serial data for SONET/SDH, ATM,
CAD networks, medical and industrial imaging
CLC016
TOP VIEW234 282726
MUTEV
ARS
SER
ACQ/WR
VEE
VCC
DDI
DDI
SCO
RD1
RD0
SCO
SDO
SDO
VEE
DDI
DDI
MUTE
SDO
SDO
SCO
SCO
CARS
SER
RTN
ACQ/WR
AUTO
1kΩ
0.1μF
CLC016DataOut
ClockOut
DataIn
Typical
Application:
Four-Rate Clock and
Data Recovery with
Automatic Rate
Selection
Pinout
General DescriptionThe Comlinear CLC016 is a low-cost, monolithic, data retiming
phase-locked loop (PLL) designed for high-speed serial clock
and data recovery. The CLC016 simplifies high-speed data
recovery in multi-rate systems by incorporating auto-rate select
(ARS) circuitry on chip. This function allows the user to config-
ure the CLC016 to recognize up to four different data rates and
automatically adjust to provide accurate, low-jitter clock and data
recovery. A single resistor is used to set each data rate anywhere
between 40Mbps and 400Mbps. No potentiometers, crystals, or
other external ICs are required to set the rate.
The CLC016 has output jitter of only 130pspp at a 270Mbps data
rate and 0.25% fractional loop bandwidth. Low phase detector
output offset and low VCO injection combine to ensure that the
CLC016 does not generate bit errors or large phase transients in
response to extreme fluctuations in data transition density. The
result is improved performance when handling the pathological
patterns inherent in the SMPTE 259M video industry standard.
The carrier detect and output mute functions may be used
together to automatically latch the outputs when no data is
present, preventing random transitions. The external loop filter
allows the user to tailor the loop response to the specific
application needs. The CLC016 will operate with either +5V or
-5.2V power supplies. The serial data inputs and outputs, as well
as the recovered clock outputs, allow single- or differential-ECL
interfacing. The logic control inputs are TTL-compatible.
Features Retimed data output Recovered clock output Auto and manual rate select modes Four user-configurable data rates No potentiometers required External loop bandwidth control Frequency detector for lock acquisition Carrier detect output Output MUTE function Single supply operation: +5V or -5.2V Low cost
Key Specifications Low jitter: 130pspp @ 270Mbps, 0.25%
fractional loop bandwidth (0.675MHz) High data rates: 40Mbps – 400Mbps Low supply current: 100mA, including
output biasing Flexible fractional loop bandwidth:
from 0.05% to 0.5%
Output Data and Clock, Differential800mV/div
500ps/div
Data Rate: 270Mbps
August 1996
Comlinear CLC016Data Retiming PLL
with
Automatic Rate Selection
