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CHL8326-CHL8328-CHL8328-00CRT-IR3536MTRPBF
Dual Loop, 5+1 multiphase VR12/AMD PWM controller for high efficiency, highly accurate VR solutions
International
TOR Rectifier
ligNW) 38
Digital Multi-Phase Buck Controller (til(llfagt .
FEATURES
q 6-phase & 8-phase dual output PWM Controller
q Phases are flexibly assigned between Loops 1 & 2
q Intel© VR12, AMDo 3.4MHz SVI/PVI & Memory
q Overclocking & Gaming Mode with Vmax setting
. Switching frequency from 200kHz to 1.2MHz per
0 IR Efficiency Shaping Features including Variable
Gate Drive and Dynamic Phase Control
q Programmable l-phase or 2-phase for Light Loads
and Active Diode Emulation for Very Light Loads
q IR Ada ptive Transient Algorithm (ATA) on both loops
minimizes output bulk capacitors and system cost
q Auto-Phase Detection with auto-compensation
o Per-Loop Fault Protection: OVP, UVP, OCP, OTP, CFP
q |2C/SMBus/PMBus system interface for telemetry
of Temperature, Voltage, Current & Power for
both loops
q Non-Volatile Memory (NVM) for custom
configuration
q Compatible with IR ATL and 3.3V Tri-state Drivers
0 +3.3V supply voltage; -20LT to 852C ambient
operation
q Pb-Free, RoHS, 7x7 48-pin & 8x8 56-pin QFN, MSL2
package
APPLICATIONS
q Intel © VR12 & AMD' SVI & PVI based systems
q DDR Memory with Vtt tracking
q Overclocked & Gaming platforms
DESCRIPTION
The |R3536/CHL8326 and |R3538/CHL8328 are dual-loop
digital multi-phase buck controllers. The |R3536/CHL8326
drive up to 6 phases and the |R3538/CHL8328 drives up to
8 phases. The |R3536/CHL8326 and |R3538/CHL8328 are
fully Intel© VR12 and AMY' SVI/PVI compliant on both
loops and provide a Vtt tracking function for DDR memory.
The |R3536/CHL8326 and |R3538/CHL8328 include the
IR Efficiency Shaping Technology to deliver exceptional
efficiency at minimum cost across the entire load range.
IR Variable Gate Drive optimizes the MOSFET gate drive
voltage based on real-time load current. IR Dynamic Phase
Control adds/drops phases based upon load current.
The |R3536/CHL8326 and |R3538/CHL8328 can be
configured to enter 1-phase operation and active diode
emulation mode automatically or by command.
IR's unique Adaptive Transient Algorithm (ATA), based on
proprietary non-Iinear digital PWM algorithms, minimizes
output bulk capacitors.
The |2C/PMBus interface can communicate with up to 16
|R3536/CHL8326 and |R3538/CHL8328 based VR loops.
Device configuration and fault parameters are easily
defined using the IR Intuitive Power Designer (DPDC) GUI
and stored in on-chip NVM.
The |R3536/CHL8326 and |R3538/CHL8328 provides
extensive OVP, UVP, OCP and OTP fault protection and
includes thermistor based temperature sensing with
VR_HOT signal.
NVM storage saves pins and enables a small package size.
The |R3536/CHL8326 and |R3538/CHL8328 also include
numerous features like register diagnostics for fast design
cycles and platform differentiation, truly simplifying
VRD design and enabling fastest time-to-market with its
"set-and-forget" methodology.
PIN DIAGRAM
Figure I: |R3536/CHL8326 Package Top View
CHL8325
48 Pln 7x7 OFN
Top View
cnuaza
" Pin axe am
Top View
Figure 2: IR3538/CHL8328 Package Top View
June 21, 2013 I FINAL I V1.09
International
TOR Rectifier
Digital Multi-Phase Buck Controller Cil(llfagt .
li%NW) 38
ORDERING INFORMATION
CHL832 -
IR353C1N1 Cl El
P/PBF - Lead Free
TR - Tape & Reel /TY - Tray
yy - Configuration File ID
xx - Customer ID
Package Type (QFN)
6: IR3536
8: IR3538
T-Tape & Reel /TY - Tray
R - Package Type (QFN)
C - Operating Temperature,
Commercial
xx - Configuration File
Part -
6: CH L8326
8: CH L8328
VFIXENiPSIZ
VFLREADY‘ 1
PWRGD2
VFLREADY A,
1 PWR‘OK
VINSEN Ci,
CHL8326
48 Pin 7x7 QFN
Top View
_ _ PWMS
- PWM
- VAR_GATE
PSI' / vu3[5]Z
GPO_A' / CBOUT2
N W m k 0 x .
P- S: 4 F- - 4 Cl
Q Q 9 TE 2 ff, DI , dig we
> >I , Tit, a a' g m t'rt 9i
i- g gnaw m'w SEIO‘E
E m M2 si E Cl mo
at J" J" I U2 2 B“
I E Q > I "
> o D > I
m >l pl tf E
Figure 3: lR3536/CHL8326 Package Top View, Enlarged
Packin
'dll" fitamlIliihT
TR=3000 IR3536MTRPBF
QFN Default
TY=2600 IR3536MTYPBF
TR=3000 IR3538MTRPBF
QFN Default
TY=2600 IR3538MTYPBF
QFN TR=3000 m3S36MxxvvTRp1 Customer Configuration
QFN TR=3000 m3S38MxxvvTRp1 Customer Configuration
Notes:
I. Customer Specific Configuration File, where
xx = Customer ID and yy = Configuration File
(Codes assigned by IR Marketing).
Packinthv 65mm
QFN T=3000 CHL8326-00CRT
TY=2600 CHL8326-00CRTY
QFN T=3000 CHL8326-xxCRTl
QFN T=3000 CHL8328-OOCRT
TY=2600 CHL8328-00CRTY
QFN T=3000 CHL8328-xxCRT1
N otes:
1. "xx" indicates a customer specific configuration file.
“ IRTNa
" IRTNQ
A ISENS
T 152m
A IHTNS
VFIXEN_PS|2 _ VSELU
VSEN V 'r:llir, VRTN_L2
CHL8328
56 Pin 8x8 QFN
Top View
VRTN . - PWM8
FIRES _ wa
TSEN . PWMS
VIBA _ PWMS
'r:llir, PWNM
VR_READV L2;
/ PWROK PWM3
GPO PWMZ
VINSEN _
ENABLE
VAR GATE
VFI_HOT
6MB mo U
5MB CLK
VHHOTJC Hm
‘InleI/MPcL mode
‘AMD mode
5M8 ALERT»
GPO A' / CBOUTz
Psl(MPoL)'/VID 2
sv_ALEm' /VID
sv ADDR GPO
PM ADDFLGPO
PM ADDR vu:
SV_CLK’ /svc VID
sv Dlo’ /svn VID
Figure 4: |R3538/CHL8328 Package Top View, Enlarged
June 21, 2013 I FINAL I V1.09
