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CHL8318-CHL8318CRT
8 phase VR11.1 multiphase PWM controller for high efficiency solutions
62hhid).,
Semiconductor
PRODUC T BRIEF
DIGITAL MULTI-PHASE BUCK CONTROLLER
CHL8318
FEATURES
. Intel VR11.x compliant Digital PWM Controller
. Programmable 1-phase to 8-phase operation
. Configurable switching frequency from 200 kHz to
1MHz per phase with accuracy better than 2%
. Customized Digital Over-Clocking Features
0 Easy-to-use SMBus Gamer command
C) Gamer VID control up to 2.3V, Gamer Vmax,
VID Override or Track, Digital Load-Line Adjust,
Gamer OC/OVP, Gamer OFF pin, Gamer OTP
o CHiL Efficiency Shaping Features
C) Variable Gate Drive
C) Dynamic Phase Control
. 1-phase to 4-phase PSI for Light Loads
. Adaptive Transient Algorithm minimizes output bulk
capacitors
. Designed for use with coupled inductors
o Enables Thermal Phase Balancing
o SMBus Fault Indicators: OVP, UVP, OCP, OTP
. SMBus interface for configuring and monitoring; SMBus
commands include monitoring input current and power
0 Compatible with CHiL ATL Drivers and tri-state Drivers
. Nine bytes of NVM storage available for customer use
. +3.3V supply voltage; (PC to 8590 Ambient operation
. RoHS Compliant, MSL level 1 package
DESCRIPTION
The CHL8318 is a 8-phase digital synchronous buck
controller for core regulation of high-performance INTEL®
VR11.1 and VR11.0 platforms. The CHL8318 is fully
compliant with VR11.1 including Power Status Indicator
(PSI) and for improved light load efficiency and accurate
current output (IMON).
The CHiL CHL8318 includes a customized set of digital
over-clocking features which require no external
components. Gaming applications can use the SMBus
interface to place the VRD into "Gamer Mode". Gamer Mode
features include Extended Gamer VID up to 2.3V with 6.25
mV resolution, Gamer Vmax, CPU VID Override or Track,
Digital Load-Line adjust, Gamer OC/OVP and Gamer OFF
The CHL8318 deploys a number of efficiency shaping
features. The CHL8318 can be configured to optimize
MOSFET gate drive versus load current, PSI can be
programmed to be up to four phases for optimum light-Ioad
efficiency, and the controller can autonomously add/drop
phases in Iow-current and mid-current regions to deliver
90+% efficiency across the entire load range.
CHiL's unique Adaptive Transient Algorithm, based on non-
linear digital PWM algorithms, minimizes output bulk
capacitors. Coupled inductor mode of operation allows two
phase PSI and add/drop of phases which are 180°out of
phase for further improvement in transient response and
form factor.
CHL8318 supports three NTC temperature sensors to report
temperature and trigger VR HOT and OTP faults. Digital
thermal balancing allows proportional current imbalance
between phases.
56 55 54 53 52 51 50 49 48 47 46 45 44 43
RCSP I 1 © 42 3 IRTN8 The CHL8318 provides extensive OVP, UVP, OCP and OTP
RCSM C 2 41 . ISEN8 fault protection. Device and fault configuration parameters
J,r, E 3 :3 _,", VCC are easily defined using the CHiL Intuitive Power Designer
VRTN I g 38 1 mm: (IPD) GUI and stored in on-chip non-volatile memory (NVM).
SADDR/E 6 CHL8318 37 . PWMS
GAMER-OFF 56 Pin The 3-pin SMBus interface can be used to monitor a variety
IMON I 7 8mmx8mm 36 . PWMS .
RRES C 8 QFN 35 . PWM4 of operating parameters on up to seven CHL8318 based
VINSEN I 9 TOP VIEW 34 3 PWM3 VRs. The controller includes a unique sensorless and
TSEN1 C IO 33 . PWM2 lossless input current monitoring capability.
TSEN2 C 11 32 . PWM1
TSENS C 12 31 1 NC The CHL8318 truly simplifies VRD design and enables
EN C 13 so . VCC fastest time-to-market with its "set-and-forget" methodology.
V18A re, 29 . VAR_GATE
1516171819 20 2122 23 24 25 26 27 28
at < -l , ts a, in v m N T- o >- _
i:, 8 g E E E E E E E E E fi, El q lntel(D VR11.x CPU VRD and VRM; DDR Memory
4 cc 0:
g m' > a High Performance Desktops and Servers
q Over-clocking and High-Efficiency Applications
Figure 1. CHL8318 56 Pin QFN Package
Trademarks and registered trademarks are the property of the respective One Highwood Drive, Tewksbury, MA 01876
owners. Page 1 of 4 Tel: o1(978F640-0011
www.chilsemi.com
PB0006 Rev. 1.00, October 26, 2009 © 2009 CHiL Semiconductor Corp. All rights reserved
cage", PRODUCT BRIEF CHL8318
DIGITAL MULTI-PHASE BUCK CONTROLLER
FUNCTIONAL BLOCK DIAGRAM
RRES V18A 3.3V
VID1 1 .8V LDO
VID3 VID decode
VID4 and DAC
Reference
; Digital Processor
Controller
Voltage I PWM1
Error PWM2
ADC PWM3
1 Transient PWM PWM4
Controller Generator l PWMS
VCPU —>
ISEN3 _
IRTN3 _
ISEN5 Channel Current Sense
IRTN5 _ Current
ISEN6 _ Balance
RCSP -
Monitor 4 '
TSEN1 ADC
VINSEN
SADDR/
GAMEFLOFF
SDA SMBus A
SCL Interface -_ V l
SALERT VRHOT VR_Ready GND
l VAR_GATE
Oscillator, NVM
State Control, and Current
Monitoring Monitor
4' IMON
V V V V V V HWHHWVF
Figure 2. Functional Block Diagram
€515;me Page 2 of 4 PB0006
Rev. 1.00, October 26, 2009
