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CHL8225G-00CRT
Dual loop, 4+1 multiphase PWM controller for graphics processor VR solutions with multiple input rail control
International
TOR Rectifier
Digital Multi-Phase Buck Controller
GH BIEWi) 8G
FEATURES
q S-phase & 8-phase dual output PWM Controller
with phases flexibly assigned between Loops 1 & 2
. Dynamic voltage control by 2-bit parallel interface
with Gamer Mode override and Vmax setting
q Input Voltage Management for up to 3 Input
Voltages
. ICRITICAL Monitor and Phase Current Capture Mode
q Phase Switching frequency from 200kHz to 1.2MHz
q IR Efficiency Shaping Features including Variable
Gate Drive, Dynamic Phase Control
q Programmable 1-phase or 2-phase for Light Loads
and Active Diode Emulation for Very Light Loads
q IR Adaptive Transient Algorithm (ATA) minimizes
output bulk capacitors and system cost
q Per-Loop Fault Protection: OVP, UVP, OCP, OTP
o |2C/SMBus/PMBus system interface for telemetry of
Temperature, Voltage, Current & Power for both
q Non-Volatile Memory (NVM) for custom
configuration
. Compatible with IR ATL and 3.3V tri-state Drivers
q +3.3V supply voltage; 09C to 859C ambient
operation
q Pb-Free, RoHS, 6x6 40-pin & 8x8 56-pin QFN, MSL2
package
APPLICATIONS
o Multiphase GPU systems
DESCRIPTION
The CHL8225G/8G are dual-loop, digital multi-phase buck
controllers. The CHL8225G drives up to 5 phases and the
CHL8228G drives up to 8 phases. They feature Input
Voltage Management allowing up to 3 input voltages to be
monitored to ensure adequate power is delivered to the
load. Dynamic voltage control is provided by 4 registers
which are programmed through |2C/SMBus/PMBus and
then selected using a 2-bit parallel bus for fast access.
The CHL82256/8G includes the IR Efficiency Shaping
Technology to deliver exceptional efficiency at minimum
cost across the entire load range. IR Variable Gate Drive
optimizes the MOSFET gate drive voltage as a function of
real-time load current. IR Dynamic Phase Control adds and
drops phases based upon load current. The CHL82256/8G
can be configured to enter 1-phase operation and active
diode emulation based upon load current or by command.
IR's unique Adaptive Transient Algorithm (ATA), based on
proprietary non-Iinear digital PWM algorithms, minimizes
output bulk capacitors.
The |2C/PMBus interface can communicate with up to 16
CHL8225G/8G-based VR loops. Device configuration and
fault parameters are defined using the IR Digital Power
Design Center (DPDC) GUI and stored in on-chip NVM.
The CHL8225G/8G provides extensive OVP, UVP, OCP and
OTP fault protection and includes thermistor based
temperature sensing with VRHOT signal. The CHL8225G/8G
includes numerous features like register diagnostics for
fast design cycles and platform differentiation, simplifying
VRD design and enabling fastest time-to-market with its
"set-and-forget" methodology.
PIN DIAGRAM
ncsp if,
HCSM jff,
v00 :3
VSEN 1:1:
VRTN Cir, CHL8225G
- 40 Pin 6x6 ttFN
nnss fi_) TopView
TSEN ",1
VR_READY_U :1
VR_READY_L2 Citi'; _____
VIDSEL L2
VAFLGATE u-v
V|NSEN AUX! _
RCSP_L2
RcsM_L2
1": VSEN_L2
VRTN_L2
Lii, PWM3
Lii, PWMe
" _ PWM!
Figure 1: CHL8225G Package Top View
ism j]] [ff ISENT
ncsp yr, -rff. ncsmz
Raw :3 g: mm
VCC 333 '.Tf VCU'
won :3 =1: mm
VSEN yr, iii: WW
Wm :3 CHLBZZBG i: W!
-r 56P|n8x80FN -"
Wis P..) Top View _'.. PWM
TSEN ji) g: 17st
m. :3 Cay. Pst
vumw :3 1: PW.
mem 3:] -"'.' pm
my ctr, PWM
mm F) 'rr, PWMI
Figure 2: CHL8228G Package Top View
il June 21,2013 I FINAL I v1.12
International
TOR Rectifier Digital Multi-Phase Buck Controller (tRIlfgiEWhWE
ORDERING INFORMATION
CHL822ClG- Packingczty fitimf2lgiihg
QFN T=3000 CHL8ZZSG-00CRT
T -Tape & Reel /TY - Tray TY=4900 CHL8225G-00CRTY
R- Package Type (QFN) QFN T=3000 CHL8225G xxCRT
QFN T=3000 CHL8228G-00CRT
C - Operating Temperature TY=2600 CHL8228G-00CRTY
(Commercial Standard) QFN T=3000 CHL8228G-xxCRT1
xx - Configuration File Notes:
Part Number I. xx indicates customer specific configuration file.
5: CHL8225G
8: CHL8228G
E Lo E E E Ln E Lo E E -
050' ',39i, £38] (37'," (36'," £35; " (33'," E32: 531; SEN: i;
"-- -- "-- -- -- ~-- - - HcsP '
RCSP "If: /' ------------ j Lif, Rcsuz mm YL
RCSM , l 21mm VCU :1
l -""l
VCC 15:: : E Lif, VCC VRHOT (d
VSEN Yff, : l Lif. VSEN_L2 VSEN :1
- , u - vam YY) CHL8228G
VRTN -fiff; t CHL8225G I ryf. VRTN_L2 "T") 56 P". QFN
If; l 40 Pin6x6 QFN l '_’_'_' ms 3.: TopView
RRES A l l Top View l L352 PWM5 TSEN hy,
TSEN Cty, l l , Ci. PWM4 won 391
V18A 33:] E l Liii. PWM3 VFLREADY_LI ii]
I VR READYL2 Tf)
VR_READCLI 21:32:: l l L21 PWM2 - - Il
- l 41 GND I v___ EN_L2 )1;
VR_READY_L2 .19.: L -_-_-_-_-_--_-_V u Lg]. PWM1 VINSEN Tf)
F11" ',Tii, Fi: Tii, Tii [{6} T/ 51's} 5'13; '20 " " Wh' 52;;
vmsau ::
VIDSELI :_.
ENABLE _ '
-:::: I: l "sllttil I‘
-NN =.wmo¥._ Nu:
3,12: 2:: 2E)e 'ili'-iiisirrii')ti,3kC'i5ii:il.'s-'
wDJ WE 00< 'h'h,'-7, 1l'5'k'a'ii)fjjf,il)its'6,
< 0) ‘I0 22% 'gDr"u'd,'rt''t''' I
Z.% o9 mm. WWn 5 nww <
>2D S._' 22:: 95’; T s >
m. mw< ss m
tnts O > >
Figure 4: CHL8228G Top View Enlarged
Figure 3: CHL8225G Top View Enlarged
i2 June 21,2013 I FINAL I v1.12