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CGS74B303M
Octal Divide-by-2 Skew Clock Driver
TL/F/10966
CGS74B303
Octal
Divide-by-2
Skew
Clock
Driver
July 1996
CGS74B303 Octal Divide-by-2 Skew Clock Driver
General Description
These minimum skew clock driversare designedfor high
frequency Clock Generation and Support (CGS) applica-
tions. These devicesare idealfor duty cycle recovery appli-
cationswith internal frequency divide-by-2 circuitry.Thede-
vices guarantee minimum skew acrossthe outputsofagiv- device. Skew parametersare also providedasa means measure duty cycle requirementsas those foundin high
speed clocking systems.
Functional Description
The CGS74B303 contains eight flip-flops designedto have
low skew between outputs.The eight outputs(six in-phase
with CLKandtwo out-of-phase) toggleon successive CLK
pulses. PREand CLR inputsare providedtosetQandQ
outputs highorlow independentof CLKpin.
Features Clock Generation and Support (CGS) Devices idealfor
high frequency signal generationor clock distribution
applications Fabricatedon National’s Advanced Bipolar FASTTMLSl
process1ns pin-to-pin output skew Specificationfor transition skewto meet duty cycle
requirements Current sourcing24mAand current sinkingof48mA Low dynamic power consumption above20 MHz Guaranteed4kV ESD protection
Logic Diagram Connection Diagram
TL/F/10966–3
PinAssignment
SOlC(M)
TL/F/10966–1
Pin Description
Pin Names Description
CLK Clock Input
Q0–Q7 Outputs
PRE Preset
CLR Clear
Truth Table
Inputs Outputs
CLR PRE CLK Q0–Q5 Q6–Q7 X L H X H L X L* L* u Q Q L Q Q
*Thisstatewillnot persist when CLR/PRE returnstohigh.
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
FASTTMisa trademarkof National SemiconductorCorporation.
C1996National SemiconductorCorporation RRD-B30M86/Printed inU.S.A. http://
