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CGS702V
Commercial Low Skew PLL 1-to-9 CMOS Clock Driver with Improved EMI
TL/F/12386
CGS702V
Commercial
Low
Skew
PLL
CMOS
Clock
Driver
with
Improved
EMI
September 1995
CGS702V
Commercial Low Skew PLL1 to9 CMOS Clock Driver
with Improved EMI
General Description
The CGS702isan off-the-shelf clock driver specificallyde-
signedfor today’s high speed processors.It provideslow
skew outputs whichare producedat different frequencies
from three fixed input references.The CGS702isa reduced
EMI versionofthe CGS700. The XTALIN inputpinisde-
signedtobe drivenfromthree distinct crystal oscillatorsrun-
ningat25 MHz,33 MHzor40 MHz.
The PLL, usinga charge pumpandan internal loop filter,
multipliesthis input frequencyto createa maximum output
frequencyof four timesthe input.
The device includesa TRI-STATEÉ controlpinto disable
the outputs whilethePLLisstillin lock. This function allows
testingthe board without havingtowaitto acquirethe lock
oncethe testingis complete. (Continued)
Features Reduced EMI comparedto CGS700 (referto EMI
characteristics) Guaranteed and tested: 500ps pin-to-pin skew (TOSHL
and TOSLH)on1x outputs PentiumTM and PowerPCTM compatible Output bufferof nine driversfor large fanout25 MHz–160 MHz output frequency range Outputs operatingat4x,2x,1xofthe reference
frequencyfor multi-frequencybus applications Selectable output frequency Internal loop filterto reduce noise and jitter Separate Analogand digital VCCand Ground pins Low frequencytest modeby disablingthePLL Implementedon National’s Core CMOS process Symmetric output current drive:
a30 mA/b30mA IOL/IOH 28-pin PCCfor optimum skew performance Guaranteed2kV ESD protection
Connection Diagram
Pin Assignmentfor PLCC
TL/F/12386–1
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
PentiumTMis atrademarkofIntel Corporation.
PowerPCTMisa trademarkof InternationalBusiness Machines Corporation.
Pin Description
PLCC Package
Pin Name Description
1VCC DigitalVCC SKWSEL SkewTestSelectorPin CLK4 4x Clock Output
4VCC DigitalVCC XTALIN Crystal OscillatorInput GND DigitalGround CLK1Ð0 1x Clock Output
8VCC DigitalVCC CLK1Ð1 1x Clock Output GND DigitalGround CLK1Ð2 1x Clock Output TRI-STATE OutputTRI-STATE Control SKWTST SkewTestingPin CLK1Ð3 1x Clock Output GND DigitalGround CLK1Ð4 1x Clock Output VCC DigitalVCC EXTCLK ExternalTestClock GNDA AnalogGround VCCA AnalogVCC EXTSEL ExternalClockMUXSelector GND DigitalGround CLK1Ð5 1x Clock Output VCC DigitalVCC CLK1Ð6 1x Clock Output CLK1SEL CLK1Multiplier Selector GND DigitalGround CLK2 2x Clock Output
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
