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CGS701ATV-CGS701AV
Industrial Low Skew PLL 1 to 8 CMOS Clock Driver
TL/F/11920
CGS701AV
Commercial
Low
Skew
PLL
CMOS
Clock
Driver
CGS701ATV
Industrial
Low
Skew
PLL
CMOS
Clock
Driver
December 1995
CGS701AV
Commercial Low Skew PLL1 to8 CMOS Clock Driver
CGS701ATV
Industrial Low Skew PLL1 to8 CMOS Clock Driver
General Description
CGS701Aisanoffthe shelf clock driver specificallyde-
signedfor today’s high speed designs.It provideslow skew
outputs whichare producedat different frequencies from
three fixed input references. The XTALIN inputpinisde-
signedtobe driven froma25 MHz–40 MHz crystal oscilla-
tor.
The PLL, usinga charge pumpandan internal loop filter,
multipliesthis input frequencyto createa maximum output
frequencyof four timesthe input.
The device includesa TRI-STATEÉ controlpinto disable
the outputs. This feature allowsforlow frequency functional
testingand debugging.
Also included, isan EXTSELpinto allow testingthe chipvia externalsource.The EXTSELpin, oncesetto high,caus-the External-ClockÐMUXto changeits input fromthe
outputofthe VCOand Countertothe external clock signal
providedvia SKWTST inputpin. (continued)
Features Guaranteed:
400ps pin-to-pin skew (tOSHL and tOSLH)on1X
outputs. PentiumÉ and PowerPCTM compatible g300ps propagation delay Output bufferof eight driversfor large fanout25 MHz–160 MHz output frequency range Outputs operatingat4X,2X,1Xofthe referencefre-
quencyfor multifrequencybus applications Selectable output frequency Internal loop filterto reduce noise and jitter Separate analogand digital VCCand ground pins Low frequencytest modeby disablingthePLL Implementedon National’s Core CMOS process Symmetric output current drive: a30/b30mA IOL/IOH Industrial temperatureof b40§Cto a85§C 28-pin PLCCfor optimum skew performance Guaranteed2k volts ESD protection
Connection Diagram
Pin Assignmentfor PLCC
TL/F/11920–1
Pin Description
PLCC Package
Pin Name Description
1VCC DigitalVCC FBKIN FeedbackInputPin CLK4 4XClock Output
4VCC DigitalVCC XTALIN Crystal OscillatorInput GND DigitalGround FBKOUT FeedbackOutputPin
8VCC DigitalVCC CLK1Ðl 1XClock Output GND DigitalGround CLK1Ð2 1XClock Output TRI-STATE OutputTRI-STATE Control SKWTST SkewTestingPin CLK1Ð3 1XClock Output GND DigitalGround CLK1Ð4 1XClock Output VCC DigitalVCC SKWSEL SkewTestSelectorPin GNDA AnalogGround VCCA AnalogVCC EXTSEL ExternalClockMUXSelector GND DigitalGround CLK1Ð5 1XClock Output VCC DigitalVCC CLK1Ð0 1XClock Output CLK1SEL CLK1Multiplier Selector GND DigitalGround CLK2 2XClock Output
PentiumÉisa registered trademark ofIntelCorporation.
PowerPCTMisa trademarkof InternationalBusiness Machines Corporation.
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1996National SemiconductorCorporation RRD-B30M106/Printed inU.S.A. http://
