CDCVF2510PW ,3.3-V Phase-Lock Loop Clock DriverSCAS638C–JULY 2001–REVISED APRIL 2006DISSIPATION RATING TABLEDERATINGBOARD T ≤ 25°C POWER T = 70°C ..
CDCVF2510PW ,3.3-V Phase-Lock Loop Clock DriverBLOCK DIAGRAM11G31Y041Y151Y281Y391Y4151Y5161Y6**17241Y7CLKPLL*20131Y8FBIN*211Y923AVCC12FBOUTAVAILAB ..
CDCVF2510PW ,3.3-V Phase-Lock Loop Clock DriverMAXIMUM RATINGS(1)over operating free-air temperature range (unless otherwise noted)UNIT(2)AV Suppl ..
CDCVF2510PWG4 ,3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 85FEATURESPW PACKAGE• Designed to Meet and Exceed PC133 SDRAM(TOP VIEW)Registered DIMM Specification ..
CDCVF2510PWR ,3.3-V Phase-Lock Loop Clock DriverSCAS638C–JULY 2001–REVISED APRIL 2006FUNCTION TABLEINPUTS OUTPUTS1YG CLK FBOUT(0:9)X L L LL H L HH ..
CDCVF2510PWRG4 ,3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 85SCAS638C–JULY 2001–REVISED APRIL 2006TERMINAL FUNCTIONSTERMINALTYPE DESCRIPTIONNAME NO.Clock input. ..
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CDCVF2510PW-CDCVF2510PWG4-CDCVF2510PWR-CDCVF2510PWRG4
3.3-V Phase-Lock Loop Clock Driver
VCC
FBIN
FBOUT
NOT RECOMMENDED
FOR NEW DESIGNS
USE CDCVF2510A AS
A REPLACEMENT
DESCRIPTION Availablein Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications Distributes One Clock Inputto One Bankof Outputs External Feedback (FBIN) TerminalIs Usedto
Synchronize the Outputsto the Clock Input 25-Ω On-Chip Series Damping Resistors No External RC Network Required Operatesat 3.3VThe CDCVF2510isa high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.It usesa
phase-lock loop (PLL)to precisely align,in both frequency and phase, the feedback (FBOUT) outputto the clock
(CLK) input signal.Itis specifically designed for use with synchronous DRAMs. The CDCVF2510 operatesata
3.3-V VCC.It also provides integrated series-damping resistors that makeit ideal for driving point-to-point loads.
One bankof10 outputs provides10 low-skew, low-jitter copiesof CLK. Output signal duty cycles are adjustedto
50%, independentof the duty cycleat CLK. Outputs are enabledor disabled via the control (G) input. When the inputis high, the outputs switchin phase and frequency with CLK; when theG inputis low, the outputs are
disabledto the logic-low state.
Unlike many products containing PLLs, the CDCVF2510 does not require external RC networks. The loop filter
for the PLLis included on-chip, minimizing component count, board space, and cost.is based on PLL circuitry, the CDCVF2510 requiresa stabilization timeto achieve phase lockof theto the reference signal. This stabilization timeis required following power up and applicationofa signalat CLK,or following any changesto the PLL referenceor feedback signals.
CDC509/516/2509/2510/2516 (SLMA003) and Using CDC2509A/2510A PLL With Spread Spectrum Clocking
