CDCVF2510APWR ,3.3-V Phase-Lock Loop Clock Driver with Power Down ModeTerminal FunctionsTERMINALTYPE DESCRIPTIONNAME NO.Clock input. CLK provides the clock signal to be ..
CDCVF2510PW ,3.3-V Phase-Lock Loop Clock DriverSCAS638C–JULY 2001–REVISED APRIL 2006DISSIPATION RATING TABLEDERATINGBOARD T ≤ 25°C POWER T = 70°C ..
CDCVF2510PW ,3.3-V Phase-Lock Loop Clock DriverBLOCK DIAGRAM11G31Y041Y151Y281Y391Y4151Y5161Y6**17241Y7CLKPLL*20131Y8FBIN*211Y923AVCC12FBOUTAVAILAB ..
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CDCVF2510PWG4 ,3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 85FEATURESPW PACKAGE• Designed to Meet and Exceed PC133 SDRAM(TOP VIEW)Registered DIMM Specification ..
CDCVF2510PWR ,3.3-V Phase-Lock Loop Clock DriverSCAS638C–JULY 2001–REVISED APRIL 2006FUNCTION TABLEINPUTS OUTPUTS1YG CLK FBOUT(0:9)X L L LL H L HH ..
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CDCVF2510APW-CDCVF2510APWG4-CDCVF2510APWR
3.3-V Phase-Lock Loop Clock Driver with Power Down Mode
CDCVF2510A www.ti.com ............................................................................................................................................... SCAS764C–MARCH 2004–REVISED FEBRUARY 2009 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE 1 FEATURES APPLICATIONS • DRAM Applications • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification • PLL Based Clock Distributors Rev. 1.1 • Non-PLL Clock Buffer • Spread Spectrum Clock Compatible PW PACKAGE • Operating Frequency 20 MHz to 175 MHz (TOP VIEW) • Static Phase Error Distribution at 66 MHz to 166 MHz is ±125 ps AGND 1 24 CLK V 2 23 AV • Jitter (cyc–cyc) at 66 MHz to 166 MHz is CC CC 1Y0 3 22 V |70| ps CC 1Y1 1Y9 4 21 • Advanced Deep Submicron Process Results in 1Y2 5 20 1Y8 More Than 40% Lower Power GND 6 19 GND Consumption vs Current Generation GND 7 18 GND PC133 Devices 1Y3 8 17 1Y7 • Auto Frequency Detection to Disable 1Y4 9 16 1Y6 Device (Power-Down Mode) V 10 15 1Y5 CC • Available in Plastic 24-Pin TSSOP G V 11 14 CC • Distributes One Clock Input to One Bank of FBOUT 12 13 FBIN 10 Outputs • External Feedback (FBIN) Terminal is Used to Synchronize the Outputs to the Clock Input • 25-Ω On-Chip Series Damping Resistors • No External RC Network Required • Operates at 3.3 V DESCRIPTION The CDCVF2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. The CDCVF2510A uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510A operates at a 3.3-V V and also provides integrated series-damping resistors that make it ideal CC for driving point-to-point loads. One bank of 10 outputs provides 10 low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Outputs are enabled or disabled via the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. The device automically goes into power-down mode when no input signal (< 1 MHz) is applied to CLK; the outputs go into a low state. Unlike many products containing PLLs, the CDCVF2510A does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDCVF2510A requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, a fixed-phase signal at CLK, or following any changes to the PLL reference or feedback signals. The PLL can be bypassed by strapping AV to ground to use as a simple clock buffer. CC 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2004–2009, Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
