CDCVF2509PW ,3.3-V Phase-Lock Loop Clock DriverThese devices have limited built-in ESD protection. The leads should be shorted together or the dev ..
CDCVF2509PWR ,3.3-V Phase-Lock Loop Clock DriverMAXIMUM RATINGS(1)over operating free-air temperature range (unless otherwise noted)UNIT(2)AV Suppl ..
CDCVF2509PWRG4 ,3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 85FEATURES • 25-Ω On-Chip Series Damping Resistors• Use CDCVF2509A (SCAS765) as a • No External RC Ne ..
CDCVF2510APW ,3.3-V Phase-Lock Loop Clock Driver with Power Down ModeFEATURES APPLICATIONS• DRAM Applications• Designed to Meet and Exceed PC133SDRAM Registered DIMM Sp ..
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CDCVF2510APWR ,3.3-V Phase-Lock Loop Clock Driver with Power Down ModeTerminal FunctionsTERMINALTYPE DESCRIPTIONNAME NO.Clock input. CLK provides the clock signal to be ..
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CDCVF2509PW-CDCVF2509PWR-CDCVF2509PWRG4
3.3-V Phase-Lock Loop Clock Driver
CLK
AVCC
VCC
2Y0
2Y1
GND
GND
2Y2
2Y3
VCC
FBIN
AGND
VCC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VCC
FBOUT
PW PACKAGE
(TOP VIEW)
1FEATURES • 25-Ω Series Damping Resistors Use CDCVF2509A (SCAS765)asa • No RC Network Required
Replacement for This Device • Operatesat 3.3V Designedto Meet and Exceed PC133
SDRAM Registered DIMM Specification APPLICATIONS
Rev. 1.1 • DRAM Spread Spectrum Clock Compatible • PLL Clock Distributors Non-PLL Clock Buffer• Operating Frequency50 MHzto 175 MHz Static Phase Error Distributionat66 MHzto
166 MHzIs ±125 ps Jitter (cyc- cyc)at66 MHzto 166 MHzIs
Typ=70 ps Advanced Deep Submicron Process
Resultsin More Than 40% Lower Power
Consumption Versus Current Generation
PC133 Devices Availablein Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications Distributes One Clock Inputto One Bankof
Five and One Bankof Four Outputs Separate Output Enable for Each Output
Bank External Feedback (FBIN) TerminalIs Used Synchronize the Outputsto the Clock
Input low-skew, low-jitter, clock driver.It usesa PLLto and phase, the feedback the clock (CLK) input signal.Itis use synchronous DRAMs.ata 3.3-V VCC.It also makeit loads. outputs provide low-jitter copiesof CLK. Outputof the enabled and 2G) inputs. When inputs are low, the outputs the state. the CDCVF2509 does external RC networks. loop component count, board and cost.
