CDCVF2509APW ,3.3-V Phase-Lock Look Clock Driver with Power DownPin FunctionsPINTYPE DESCRIPTIONNAME NO.Clock input. CLK provides the clock signal to be distribute ..
CDCVF2509APWG4 ,3.3-V Phase-Lock Look Clock Driver with Power Down 24-TSSOP 0 to 85MAXIMUM RATINGS(1)over operating free-air temperature range (unless otherwise noted)UNIT(2)AV Suppl ..
CDCVF2509APWRG4 ,3.3-V Phase-Lock Look Clock Driver with Power Down 24-TSSOP 0 to 85These devices have limited built-in ESD protection. The leads should be shorted together or the dev ..
CDCVF2509PW ,3.3-V Phase-Lock Loop Clock DriverThese devices have limited built-in ESD protection. The leads should be shorted together or the dev ..
CDCVF2509PWR ,3.3-V Phase-Lock Loop Clock DriverMAXIMUM RATINGS(1)over operating free-air temperature range (unless otherwise noted)UNIT(2)AV Suppl ..
CDCVF2509PWRG4 ,3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 85FEATURES • 25-Ω On-Chip Series Damping Resistors• Use CDCVF2509A (SCAS765) as a • No External RC Ne ..
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CLC005AJE ,ITU-T G.703 Cable Driver with Adjustable OutputsGeneral Description Key Specificationsn 650 ps rise and fall timesNational’s Comlinear CLC005 is a ..
CLC005AJE-TR13 ,ITU-T G.703 Cable Driver with Adjustable OutputsApplicationsand requires no external bias resistors. The differential in-n ITU-T G.703, Sonet/SDH, ..
CDCVF2509APW-CDCVF2509APWG4-CDCVF2509APWRG4
3.3-V Phase-Lock Look Clock Driver with Power Down
CLK
AVCC
VCC
2Y0
2Y1
GND
GND
2Y2
2Y3
VCC
FBIN
AGND
VCC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VCC
FBOUT
PW PACKAGE
(TOP VIEW)
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH POWER DOWN DRAM• Operating Frequency20 MHzto 175 MHz PLL Clock Distributors• Static Phase Error Distributionat66 MHzto Non-PLL Clock Buffer166 MHzIs ±125 ps Jitter (cyc- cyc)at60 MHzto 175 MHzIs
Typ=65 ps Advanced Deep Submicron Process
Resultsin More Than 40% Lower Power
Consumption Versus Current Generation
PC133 Devices Auto Frequency Detectionto Disable
Device (Power-Down Mode) Availablein Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications Distributes One Clock Inputto One Bankof
Five and One Bankof Four Outputs Separate Output Enable for Each Output
Bank External Feedback (FBIN) TerminalIs Used Synchronize the Outputsto the Clock
Input high-performance, low-skew, low-jitter, (PLL) clock driver.It usesa PLL frequency and phase, the feedback the clock (CLK) input signal.Itis DRAMs.ata 3.3-V VCC.It also makeit loads.of four outputs provideof CLK. Output independentof the duty CLK. Eachofor
disabled separately and 2G) inputs. When the are high,G inputs are low, the outputsto the logic-low The mode whenno input signalis applied CLK; the the CDCVF2509A does component count, board and cost.
