CDCVF25081PWR ,1:8 3.3-V Phase Lock Loop Clock Drivermaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage range, V ..
CDCVF25081PWR ,1:8 3.3-V Phase Lock Loop Clock Drivermaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage range, V ..
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CLC005AJE ,ITU-T G.703 Cable Driver with Adjustable OutputsGeneral Description Key Specificationsn 650 ps rise and fall timesNational’s Comlinear CLC005 is a ..
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CDCVF25081D-CDCVF25081DR-CDCVF25081PW-CDCVF25081PWG4-CDCVF25081PWR
1:8 3.3-V Phase Lock Loop Clock Driver
Distributes One Clock Input to Two Banksof Four Outputs Auto Frequency Detection to Disable
Device (Power Down Mode) Consumes Less Than 20 μA in Power Down
Mode Operates From Single 3.3-V Supply Industrial Temperature Range –40°C to
85°C 25-Ω On-Chip Series Damping Resistors No External RC Network Required Spread Spectrum Clock Compatible (SSC) Available in 16-Pin TSSOP or 16-Pin SOIC
Packages
descriptionThe CDCVF25081 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a PLL to
precisely align, in both frequency and phase, the output clocks to the input clock signal. The CDCVF25081
operates from a nominal supply voltage of 3.3 V. The device also includes integrated series-damping resistors
in the output drivers that make it ideal for driving point-to-point loads.
Two banks of four outputs each provide low-skew, low-jitter copies of CLKIN. All outputs operate at the same
frequency. Output duty cycles are adjusted to 50%, independent of duty cycle at CLKIN. The device
automatically goes into power-down mode when no input signal is applied to CLKIN and the outputs go into a
low state. Unlike many products containing PLLs, the CDCVF25081 does not require an external RC network.
The loop filter for the PLL is included on-chip, minimizing component count, space, and cost.
Because it is based on a PLL circuitry, the CDCVF25081 requires a stabilization time to achieve phase lock of
the feedback signal to the reference signal. This stabilization is required following power up and application of
a fixed-frequency signal at CLKIN and any following changes to the PLL reference.
The CDCVF25081 is characterized for operation from -40°C to 85°C.
FUNCTION TABLE†CLK input frequency < 2 MHz switches the outputs to low level
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1Y1
VDD
GND
2Y0
2Y1
1Y2
VDD
GND
2Y3
2Y2
