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CDCVF2505D-CDCVF2505DR-CDCVF2505PW-CDCVF2505PWR-CDCVF2505PWRG4
PLL Clock Driver for Synch. DRAM & Gen. Purp. Apps W/Spread Spectrum Compatibility, Power Down Mode
Edge Detect
Typical <10 MHz
Power Down
3-State
1Y0
1Y1
1Y2
1Y3
CLKIN PLL 25W
25W
25W
25W
25W
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CDCVF2505SCAS640G –JULY 2000–REVISED AUGUST 2016
CDCVF2505 3.3-V Clock Phase-Lock Loop Clock Driver Features Phase-Lock Loop Clock Driver for Synchronous
DRAM and General-Purpose Applications Spread Spectrum Clock Compatible Operating Frequency: 24 MHzto 200 MHz Low Jitter (Cycle-to-Cycle):< |150 ps|
(Over 66 MHzto 200 MHz Range) Distributes One Clock Inputto One Bankof Five
Outputs (CLKOUT Usedto Tune the Input-Output
Delay) Three-States Outputs When ThereIs No Input
Clock Operates From Single 3.3-V Supply Availablein 8-Pin TSSOP and 8-Pin SOIC
Packages Consumes Less Than 100 mA (Typical)in Power-
Down Mode Internal Feedback LoopIs Usedto Synchronize
the Outputsto the Input Clock 25-Ω On-Chip Series Damping Resistors Integrated RC PLL Loop Filter Eliminates the
Need for External Components
Applications Synchronous DRAMs Industrial Applications General-Purpose Zero-Delay Clock Buffers
DescriptionThe CDCVF2505isa high-performance, low-skew,
low-jitter, phase-lock loop (PLL) clock driver. This
device usesa PLLto precisely align the output clocks
(1Y[0-3] and CLKOUT) to the input clock signal
(CLKIN) in both frequency and phase. The
CDCVF2505 operatesat 3.3V and also provides
integrated series-damping resistors that makeit ideal
for driving point-to-point loads.
One bankof five outputs provides low-skew, low-jitter
copiesof CLKIN. Output duty cycles are adjustedto percent, independentof duty cycleat CLKIN. The
device automatically goes into power-down mode
when no input signalis appliedto CLKIN.
The loop filter for the PLLsis included on-chip. This
minimizes the component count, space, and cost.
The CDCVF2505is characterized for operation from
–40°Cto 85°C.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Functional Block Diagram
