CDCV857BDGGRG4 ,2.5 V Phase Lock Loop DDR Clock Driver 48-TSSOP 0 to 70CDCV857B, CDCV857BI2.5-V PHASE-LOCK LOOP CLOCK DRIVERSCAS689A − FEBRUARY 2003 − REVISED NOVEMBER 20 ..
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CDCV857BIDGG ,2.5 V Phase Lock Loop DDR Clock Driverblock diagram3Y02Y05Y137PWRDWN6Power DownY116AVDD and Test10Y2Logic9Y220Y319Y322Y423Y446Y547Y513CLK ..
CDCV857BIDGGR ,2.5 V Phase Lock Loop DDR Clock Drivermaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage range, V ..
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CDCV857B-CDCV857BDGG-CDCV857BDGGR-CDCV857BDGGRG4
2.5 V Phase Lock Loop DDR Clock Driver
Low Jitter (cycle-cycle): ±50 ps Low Static Phase Offset: ±50 ps Low Jitter (Period): ±35 ps Distributes One Differential Clock Input to10 Differential Outputs Consumes < 100-μA Quiescent Current External Feedback Pins (FBIN, FBIN) AreUsed to Synchronize the Outputs to theInput Clocks Meets/Exceeds the Latest DDR JEDECSpec JESD82−1 DescriptionThe CDCV857B is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clockinput pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedbackclock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedbackclocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, theoutputs switch in phaseand frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state)and the PLL is shut down (low-power mode). The device also enters this low-power mode when the inputfrequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An inputfrequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, thisdetection circuit turns the PLL on and enables the outputs.
When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857B is also ableto track spread spectrum clocking for reduced EMI.
Since the CDCV857B is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.This stabilization time is required following power up. The CDCV857B is characterized for both commercial andindustrial temperature ranges.
AVAILABLE OPTIONS
FUNCTION TABLE
(Select Functions)Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
