CDCV850DGGR ,2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interfacemaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage range: V ..
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CDCV850-I , 2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2 LINE SERIAL INTERFACE
CDCV850IDGGR ,2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interfaceblock diagramVDDI3Y02Y05Y16Y110Y212SCLK2-Line Serial 910Y2Interface37LogicSDATA 20Y319Y322Y423Y446Y ..
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CDCV850-CDCV850DGGR-CDCV850DGGRG4-CDCV850IDGGR
2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface
CDCV850
2.5-V PHASE LOCK LOOP CLOCK DRIVER
WITH 2-LINE SERIAL INTERFACESCAS647D − OCTOBER 2000 − REVISED APRIL 2013
Phase-Lock Loop Clock Driver for DoubleData-Rate Synchronous DRAMApplications Spread Spectrum Clock Compatible Operating Frequency: 60 to 140 MHz Low Jitter (cyc−cyc): ±75 ps Distributes One Differential Clock Input toTen Differential Outputs Two-Line Serial Interface Provides OutputEnable and Functional Control Outputs Are Put Into a High-ImpedanceState When the Input Differential ClocksAre <20 MHz 48-Pin TSSOP Package Consumes <250-μA Quiescent Current External Feedback Pins (FBIN, FBIN) AreUsed to Synchronize the Outputs to theInput Clocks
descriptionThe CDCV850 is a high-performance, low-skew,low-jitter zero delay buffer that distributes adifferential clock input pair (CLK, CLK) to tendifferential pairs of clock outputs (Y[0:9], Y[0:9])and one differential pair of feedback clock outputs(FBOUT, FBOUT). The clock outputs are con- trolled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDATA,SCLK), and the analog power input (AVDD). A two-line serial interface can put the individual output clock pairsin a high-impedance state. When the AVDD terminal is tied to GND, the PLL is turned off and bypassed for testpurposes.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
VDDQ
GND
GND
VDDQ
SCLK
CLK
CLK
VDDI
AVDD
AGND
GND
VDDQ
GND
GND
VDDQ
GND
GND
VDDQ
SDATA
FBIN
FBIN
VDDQ
FBOUT
FBOUT
GND
VDDQ
GND
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