CDCUA877ZQLR ,1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 52-BGA MICROSTAR JUNIOR -40 to 85FEATURES • Distributes One Differential Clock Input to TenDifferential Outputs• 1.8-V/1.9-V Phase L ..
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CDCUA877ZQLR
1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 52-BGA MICROSTAR JUNIOR -40 to 85
www.ti.com
FEATURES
DESCRIPTION
CDCUA877
SCAS769A–AUGUST 2006–REVISED JUNE 2007
1.8-V PHASE LOCK LOOP CLOCK DRIVER Distributes One Differential Clock Inputto Ten
Differential Outputs•
1.8-V/1.9-V Phase Lock Loop Clock Driver for
Double Data Rate (DDRII) Applications •
52-Ball μBGA (MicroStar Junior™ BGA,
0,65-mm pitch)•
Spread Spectrum Clock Compatible External Feedback Pins (FBIN, FBIN) are Used•
Operating Frequency: 125 MHzto 410 MHz to Synchronize the Outputsto the Input•
Application Frequency: 160 MHzto 410 MHz Clockst•
Low Current Consumption: <200 mA Typ •
Meetsor Exceeds CUA877/CAU878•
Low Jitter (Cycle-Cycle): ±40
ps Specification PLL Standard for•
Low Output Skew:35 Stabilization Time <6The CDCUA877isa high-performance, low-jitter, low-skew, zero-delay buffer that distributesa differential clock
input pair (CK, CK)to ten differential pairsof clock outputs (Yn, Yn) andto one differential pairof feedback clock
outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks
(FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OEis low, the
clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continuesto maintain its locked-in
frequency. OS (output select)isa program pin that must be tiedto GNDor VDD. When OSis high, OE functions previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running.
When AVDDis grounded, the PLLis turnedoff and bypassedfor test purposes.
When both clock inputs (CK, CK) are logic low, the device entersina low power mode. An input logic detection
circuit on the differential inputs, independent from input buffers, detects the logic low level and performsina low
power state whereall outputs, the feedback, and the PLL are off. When the clock inputs transition from being
logic lowto being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the
PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within
the specified stabilization time.
The CDCUA877 ableto track spread spectrum clocking (SSC) for reduced EMI. This device operates from
–40°Cto 85°C).
AVAILABLE OPTIONS 52-Ball BGA(1)–40°Cto 85°C CDCUA877ZQL
(1) Forthe most current package and ordering information, seethe
Package Option Addendumatthe endof this document,or seethe websiteat www.ti.com.
