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CDCS503PWR
Clock Buffer / Clock Multiplier with optional SSC
1FEATURES APPLICATIONS
PACKAGE 8 7 6 5
CDCS503SSC_SEL0
SSC_SEL1
GND
VDD
OUT
BLOCK DIAGRAM
GNDIN
LVCMOS
ControlDD
SSC_SEL0
SSC_SEL1
x1 or x4
/ SSC
DESCRIPTION
CDCS503
www.ti.com.................................................................................................................................................................................................. SCAS872–MARCH 2009
Clock Buffer/Clock Multiplier With Optional SSC Consumer and Industrial Applications•
Partofa Familyof Easyto use Clock
requiring EMI reduction through SpreadGenerator Devices With Optional SSC Spectrum Clocking and/or Clock•
Clock Multiplier With Selectable Output MultiplicationFrequency and Selectable SSC SSC Controllable via2 External Pins ±0%, ±0.5%, ±1%, ±2% Center Spread Frequency Multiplication Selectable Betweenorx4 With One External Control Pin Output Disable via Control Pin Single 3.3V Device Power Supply Wide Temperature Range –40°Cto 85°C Low Space Consumption by8 Pin TSSOP
PackageThe CDCS503 isa spread spectrum capable, LVCMOS Input
multiplication. shares major functionality with the CDCS502 but utilizesa LVCMOS input stage insteadof the crystal input
stageof the CDCS502. Also an Output Enable pin has been addedto the CDCS503.
The device acceptsa 3.3V LVCMOS
The input signalis processed bya
multipliedby the factorof4.
The PLLis also ableto spread the
frequency witha triangular modulation. this, the device can generate output separate control pin canbe usedto
