CDCR83ADBQR ,Direct Rambus(TM) Clock Generator 24-SSOP -40 to 85FEATURESDBQ PACKAGE• 400-MHz Differential Clock Source for Direct(TOP VIEW)Rambus™ Memory Systems f ..
CDCR83ADBQR G4 ,Direct Rambus(TM) Clock Generator 24-SSOP -40 to 85SCAS811–AUGUST 2005TERMINAL FUNCTIONSTERMINALI/O DESCRIPTIONNAME NO.CLK 20 O Output clockCLKB 18 O ..
CDCR83ADBQRG4 ,Direct Rambus(TM) Clock Generator 24-SSOP -40 to 85SCAS811–AUGUST 2005PLL DIVIDER SELECTIONTable 1 lists the supported REFCLK and BUSCLK frequencies. ..
CDCR83DBQ ,400MHz Direct Rambus (TM) Clock Generatorblock diagramPWRDWNB S0 S1 S2 STOPBTest MUXBypass MUXByPCLKPLLCLKCLKPLLPhase CLKBBREFCLKAlignerAPAC ..
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Direct Rambus(TM) Clock Generator 24-SSOP -40 to 85
CDCR83A www.ti.com SCAS811–AUGUST 2005 DIRECT RAMBUS™ CLOCK GENERATOR FEATURES DBQ PACKAGE • 400-MHz Differential Clock Source for Direct (TOP VIEW) Rambus™ Memory Systems for an 800-MHz V IR S0 1 24 Data Transfer Rate DD REFCLK S1 2 23 • Fail-Safe Power Up Initialization V P V O 3 22 DD DD • Synchronizes the Clock Domains of the GNDP GNDO 4 21 Rambus Channel With an External System or GNDI CLK 5 20 Processor Clock PCLKM NC 6 19 • Three Power Operating Modes to Minimize SYNCLKN CLKB 7 18 Power for Mobile and Other Power-Sensitive GNDC 8 17 GNDO Applications V C 9 16 V O DD DD • Operates From a Single 3.3-V Supply and V IPD 10 15 MULT0 DD 120 mW at 300 MHz (Typ) STOPB MULT1 11 14 • Packaged in a Shrink Small-Outline Package PWRDNB S2 12 13 (DBQ) NC − No internal connection • Supports Frequency Multipliers: 4, 6, 8, 16/3 • No External Components Required for PLL • Supports Independent Channel Clocking • Spread Spectrum Clocking Tracking Capability to Reduce EMI • Designed for Use With TI's 133-MHz Clock Synthesizers CDC924 and CDC921 • Cycle-Cycle Jitter Is Less Than 50 ps at 400 MHz • Certified by Gigatest Labs to Exceed the Rambus DRCG Validation Requirement • Supports Industrial Temperature Range of –40°C to 85°C DESCRIPTION The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory applications. The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK frequencies by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects the phase difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew between PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK boundary without incurring additional latency. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DIRECT RAMBUS, Rambus are trademarks of Rambus Inc. PRODUCTION DATA information is current as of publication date. Copyright © 2005, Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
