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CDCP1803-CDCP1803RGERG4-CDCP1803RTHR-CDCP1803RTHT
1:3 LVPECL Clock Buffer with Programable Divider
(1) Thermal pad must be connected to VSS.
VDD1
VDD1
VSS 23 22 21 20 19
VDDPECL
VDDPECL V Y0 V Y2
VSS(1)
RTH PACKAGE
(TOP VIEW)VSS(1)
VDDPECL
VDDPECL
VBB 23 22 21 20 19 8 9 10 11 12 V Y0 V Y2
RGE PACKAGE
(TOP VIEW)(1) Thermal pad must be connected to VSS.
P0024-02
CDCP1803
www.ti.com SCAS727F –NOVEMBER 2003–REVISED DECEMBER 2013
1:3 LVPECL CLOCK BUFFER
WITH PROGRAMMABLE DIVIDER
Checkfor Samples: CDCP1803
1FEATURES Distributes One Differential Clock Inputto
Three LVPECL Differential Clock Outputs Programmable Output Divider for Two LVPECL
Outputs Low-Output Skew15 ps (Typical) VCC Range3 V–3.6V Signaling Rate Upto 800-MHz LVPECL Differential Input Stage for Wide Common-
Mode Range Provides VBB Bias Voltage Output for Single-
Ended Input Signals Receiver Input Threshold ±75 mV 24-Terminal QFN Package(4 mm×4 mm) Accepts Any Differential Signaling:
LVDS, HSTL, CML, VML, SSTL-2, and
Single-Ended: LVTTL/LVCMOS
DESCRIPTIONThe CDCP1803 clock driver distributes one pairof
differential clock inputs to three pairs of LVPECL
differential clock outputs Y[2:0] and Y[2:0] with
minimum skew for clock distribution. The CDCP1803 specifically designed for driving 50-Ω transmission
lines.
The CDCP1803 has three control terminals, S0, S1, output mode settings; see CDCP1803is characterizedto For usein single- CDCP1803 also terminal that can be directly
