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CDCM9102RHBR
Low Noise Two Channel 100MHz PCIe Clock Generator
CDCM9102
100MHz LVPECL
VDD
HCSL input
HCSL output
VDD
150 56
471 471
Up to 8x
100MHz
HCSL
outputs
150 56
ITTP
OTTP
IN1P
IN1N
OUT1POUT1N
OUT2POUT2N
OUT3P
OUT3N
OUT4P
OUT4N
OUT8P
OUT8N
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CDCM9102 Two Low-Noise 100-MHz Clocks (LVPECL,
LVDS,or pairof LVCMOS) Support for HCSL Signaling Levels
(AC-Coupled) Typical Period Jitter:21ps pk-pk Typical Random Jitter: 510fs RMS Output Type Setby Pins Bonus Single-Ended 25-MHz Output Integrated Crystal Oscillator Input Accepts
25-MHz Crystal Output Enable Pin Shuts Off Device and Outputs 5-mm× 5-mm 32-Pin VQFN Package ESD Protection Exceeds 2000V HBM, 500V
CDM Industrial Temperature Range (–40°Cto 85°C) 3.3-V Power Supply
Applications Reference Clock Generation for PCI Express
Gen1, Gen2, and Gen3 General-Purpose Clocking
The device supports upto PCIE gen3 andis easyto
configure and use. The CDCM9102 provides two
100-MHz differential clock ports. The output types
supported for these ports include LVPECL, LVDS,or pair of LVCMOS buffers. HCSL signaling is
supported using an AC-coupled network. The user
configures the output buffer type desiredby strapping
device pins. Additionally,a single-ended 25-MHz
clock output port is provided. Uses for this port
include general-purpose clocking, clocking Ethernet
PHYs,or providinga reference clock for additional
clock generators. All clocks generated are derived
froma single external 25-MHz crystal.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Simplified Schematic
