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CDCM61001RHBR-CDCM61001RHBT
1:1 Ultra Low Jitter Crystal-In Clock Generator
CDCM61001
www.ti.com SCAS869F –FEBRUARY 2009–REVISED JUNE 2011
One Output, Integrated VCO, Low-Jitter Clock Generator
Checkfor Samples: CDCM61001 Two Pins for Prescaler/Feedback Divider
1FEATURES Three Pins for Output Divider One Crystal/LVCMOS Reference Input Two Pins for Output SelectIncluding 24.8832 MHz, 25 MHz, and 26.5625
MHz •
Chip Enable and Device Reset Control Pins
Available•
Input Frequency Range: 21.875 MHzto
28.47 MHz •
3.3-V Core and I/O Power Supply On-Chip VCO Operatesin Frequency Rangeof •
Industrial Temperature Range: –40°C
to +85°C1.75 GHzto 2.05 GHz •
5-mm×
5-mm, 32-pin, QFN (RHB) Package•
1x Output Available: •
ESD Protection Exceeds2 kV (HBM)–
Pin-Selectable Between LVPECL, LVDS,or
2-LVCMOS; Operatesat 3.3V APPLICATIONS•
LVCMOS Bypass Output Available •
Low Jitter Clock Driver for High-End Datacom•
Output Frequency Selectable by/1,/2,/3,/4, /6, Applications Including SONET, Ethernet, Fibre/8 from the Output Divider Channel, Serial ATA, and HDTV Supports Common LVPECL/LVDS Output •
Cost-Effective High-Frequency CrystalFrequencies: Oscillator Replacement 62.5 MHz, 74.25 MHz,75 MHz, 77.76 MHz,
100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
155.52 MHz, 156.25 MHz, 159.375 MHz, DESCRIPTION187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz, The CDCM61001 isa highly versatile, low-jitter
311.04 MHz, 312.5 MHz, 622.08 MHz, frequency synthesizer that can generate low-jitter
625 MHz clock outputs, selectable between low-voltage•
Supports Common LVCMOS Output positive emitter coupled logic (LVPECL), low-voltage
Frequencies: differential signaling (LVDS), or low-voltage–
62.5 MHz, 74.25 MHz,75 MHz, 77.76 MHz, complementary metal oxide semiconductor
100 MHz, 106.25 MHz, 125 MHz, 150 MHz, (LVCMOS) outputs, froma low-frequency crystalor
155.52 MHz, 156.25 MHz, 159.375 MHz, LVCMOS input fora variety of wireline and data
187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz communication applications. The CDCM61001
Output Frequency Range: 43.75 MHzto features an onboard PLL that can be easily
683.264 MHz (See Table3) configured solely through control pins. The overall
output random jitter performanceis less than 1ps,
400 kHz RMS (from 10 kHzto20 MHz), making this devicea perfect choice for usein demanding applications such
dBc/Hzat as SONET, Ethernet, Fibre Channel, and SAN. The
625-MHz LVPECL Output CDCM61001is availableina small, 32-pin, 5-mm×
at 50%(± 5%) Divider Programming Pins: