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CDCM1804-CDCM1804RGER-CDCM1804RTHR
1:3 LVPECL Clock Buffer & Addl LVCMOS Output & Programmable Divider
www.ti.com
FEATURES
DESCRIPTIONP0025-01
VDD3
VBB
1:3
LVCMOS•
Distributes One Differential
Three LVPECL DifferentialOne LVCMOS Single-Ended•
Programmable Output DividerLVPECL Outputs and LVCMOS Low-Output Skew15 ps (Typical)
Clock-Distribution Applications
Outputs; 1.6-ns Output Skew
LVCMOS and LVPECL Transitions
Noise VCC Range3 V–3.6V Signaling Rate Upto 800-MHz
200-MHz LVCMOS Differential Input Stage for
Common-Mode Range Provides VBB Bias Voltage
Single-Ended Input Signals Receiver Input Threshold ±75
24-Terminal QFN Package Accepts Any Differential Signaling:
LVDS, HSTL, CML, VML, SSTL-2,
Single-Ended: LVTTL/LVCMOSThe CDCM1804 clock driver distributes
differential clock inputs to three
differential clock outputs Y[2:0] and
mum skew for clock distribution.
specifically designed for driving
lines. Additionally, the CDCM1804
single-ended LVCMOS output
delayed by 1.6 ns over the three
stagesto minimize noise impact
sitions. CDCM1804 has three control select different output mode settings. The are 3-level inputs and therefore allow3
