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CDCM1802RGTRG4
Clock Buffer w/Programmable Divider, LVPECL I/O + addl LVCMOS output
CDCM1802REN = 60lQ
RS1 = 0
RS0 = open
Setting for Mode 4:
EN = VDD/2
IN, IN Y0,Y0
250 MHz
125 MHz
125 MHz
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CDCM1802SCAS759C –APRIL 2004–REVISED JULY 2017
CDCM1802 Clock Buffer With Programmable Divider,
LVPECL I/O+ Additional LVCMOS Output Features Distributes One Differential Clock Inputto One
LVPECL Differential Clock Output and One
LVCMOS Single-Ended Output Programmable Output Divider for Both LVPECL
and LVCMOS Outputs 1.6-ns Output Skew Between LVCMOS and
LVPECL Transitions Minimizing Noise 3.3-V Power Supply (2.5-V Functional) Signaling Rate Upto 800-MHz LVPECL and
200-MHz LVCMOS Differential Input Stagefor Wide Common-Mode
Range Also Provides VBB Bias Voltage Outputfor
Single-Ended Input Signals Receiver Input Threshold ±75 mV 16-Pin VQFN Package (3.00 mm× 3.00 mm)
Applications Networking and Data Communications Medical Imaging Portable Test and Measurement High-end A/V
DescriptionThe CDCM1802 clock driver distributes one pairof
differential clock input to one LVPECL differential
clock output pair, Y0 and Y0, and one single-ended
LVCMOS output, Y1.Itis specifically designed for
driving 50-Ω transmission lines. The LVCMOS output delayed by 1.6 ns over the PECL output stageto
minimize noise impact during signal transitions.
The CDCM1802 has two control pins, S0 and S1,to
select different output mode settings. The S[1:0] pins
are 3-level inputs. Additionally, an enable pin ENis
provided to disable or enable all outputs
simultaneously. The CDCM1802is characterized for
operation from −40°Cto 85°C.
For single-ended driver applications, the CDCM1802
providesa VBB output pin that can be directly
connectedto the unused input asa common-mode
voltage reference.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Application Example
