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CDCLVP1212RHATTIN/a34avaiLow Jitter, 2-Input Selectable 1:12 Universal-to-LVPECL Buffer 40-VQFN
CDCLVP1212RHATTI/BBN/a1avaiLow Jitter, 2-Input Selectable 1:12 Universal-to-LVPECL Buffer 40-VQFN


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CDCLVP1212RHAT
Low Jitter, 2-Input Selectable 1:12 Universal-to-LVPECL Buffer
oltage (V)
ICM
IN,DIFF,PP
LVPECL 12
IN_MUX
OUTP[11...0]
OUTN[11...0]
VCC
VCCVCC VCC VCC VCC
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CDCLVP1212

SCAS886E –AUGUST 2009–REVISED DECEMBER 2015
CDCLVP1212 LVPECL Output, High-Performance Clock Buffer Features 3 Description

The CDCLVP1212isa highly versatile, low additive 2:12 Differential Buffer jitter buffer that can generate 12 copiesof LVPECL• Selectable Clock Inputs Through Control Terminal clock outputs from oneof two selectable LVPECL,• Universal Inputs Accept LVPECL, LVDS, and LVDS, or LVCMOS inputs for a variety of
LVCMOS/LVTTL communication applications.It hasa maximum clock
frequency upto2 GHz. The CDCLVP1212 features• 12 LVPECL Outputs an on-chip multiplexer (MUX)for selecting oneof two• Maximum Clock Frequency:2 GHz inputs that can be easily configured solely througha• Maximum Core Current Consumption:88 mA control terminal. The overall additive jitter
performanceis less than 0.1 ps, RMS from10 kHzto• Very Low Additive Jitter: <100fs, rmsin 10-kHzto MHz, and overall output skewisas lowas 25 ps,20-MHz Offset Range: making the devicea perfect choice for use in– 57fs, rms (typ)@ 122.88 MHz demanding applications.– 48fs, rms (typ)@ 156.25 MHz The CDCLVP1212 clock buffer distributes oneof two– 30fs, rms (typ)@ 312.5 MHz selectable clock inputs (IN0, IN1) to 12 pairs of 2.375-Vto 3.6-V Device Power Supply differential LVPECL clock outputs (OUT0, OUT11)
with minimum skew for clock distribution. The• Maximum Propagation Delay: 550ps CDCLVP1212 can accept two clock sources into an• Maximum Output Skew:25ps input multiplexer. The inputs can be LVPECL, LVDS,• LVPECL Reference Voltage, VAC_REF, Available or LVCMOS/LVTTL.for Capacitive-Coupled Inputs The CDCLVP1212is specifically designed for driving• Industrial Temperature Range: –40°Cto 85°C 50-Ω transmission lines. When driving the inputsin ESD Protection Exceeds2 kV (HBM) single-ended mode, the LVPECL bias voltage
(VAC_REF) should be appliedto the unused negative• Supports 105°C PCB Temperature (Measured input terminal. However, for high-speed performancewitha Thermal Pad) up to 2 GHz, differential mode is strongly• Availablein 6-mm× 6-mm QFN-40 (RHA) recommended.Package
The CDCLVP1212 is packaged ina small 40-
terminal, 6-mmx 6-mm QFN package and is2 Applications characterizedfor operation from –40°Cto 85°C.• Wireless Communications
Device Information(1)
• Telecommunications/Networking• Medical Imaging• Test and Measurement Equipment
(1) Forall available packages, see the orderable addendumat
the endofthe datasheet.
Functional Block Diagram Peak-to-Peak Voltagevs. Frequency
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