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CDCLVP111
1:10 LVPECL Buffer with Selectable Input
LVPECL
VEE
VCC VCC VCC VCC VCC
QP(9...0)
QN(9...0)
CLKP0
CLKN0
CLKP1
CLKN1
CLK_SEL
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CDCLVP111 Low-Voltage 1:10 LVPECL With Selectable Features 3 DescriptionThe CDCLVP111 Distributes One Differential Clock Input Pair differentialLVPECLto10 Differential LVPECL to ten pairs• Fully Compatible With LVECL and LVPECL outputs Supportsa Wide Supply Voltage Range from CDCLVP111
input multiplexer. The CDCLVP111 is specifically2.375Vto 3.8V
designed for driving 50-Ω transmission lines. When• Selectable Clock Input Through CLK_SEL an output pin is used, leavingit open is• Low-Output Skew (Typical15 ps)for Clock- recommendedto reduce power consumption.If onlyDistribution Applications oneof the output pinsa differential pairis used,
the other output pin be identically terminatedto– Additive Jitter Less Than1psΩ.– Propagation Delay Less Than 350ps
The VBB reference outputis usedif single-– Open Input Default State
ended input operation required.In this case, the– LVDS, CML, SSTL Input Compatible VBB pin should be connectedto CLK0 and bypassed• VBB Reference Voltage Output for Single-Ended to GND througha 10-nF capacitor.Clocking However, for high-speed performance upto 3.5 GHz,• Availableina 32-Pin LQFP and QFN Package the differential modeis strongly recommended.• Frequency Range From DCto 3.5 GHz The CDCLVP111 device is characterized for• Pin-to-Pin Compatible With MC100 Series EP111, operation from –40°Cto 85°C.ES6111, LVEP111, PTN1111
Device Information(1) Applications Designedfor Driving 50-Ω Transmission Lines• High Performance Clock Distribution
(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Functional Block Diagram
