CDCLVP110VFG4 ,1:10 LVPECL/HSTL to LVPECL Clock Driver 32-LQFP -40 to 85These devices have limited built-in ESD protection. The leads should be shorted together or the dev ..
CDCLVP110VFR ,1:10 LVPECL/HSTL to LVPECL Clock Drivermaximum ratings” may cause permanent damage to the device. These are stress ratingsonly, and functi ..
CDCLVP111 ,1:10 LVPECL Buffer with Selectable InputFeatures 3 DescriptionThe CDCLVP111 clock driver distributes one1• Distributes One Differential Clo ..
CDCLVP1212RHAT ,Low Jitter, 2-Input Selectable 1:12 Universal-to-LVPECL Buffer 40-VQFN Electrical Characteristics: LVPECL Output, at VCC = 3 V to 3.6 V ...... 10CC PCB• Added Thermal Con ..
CDCLVP1212RHAT ,Low Jitter, 2-Input Selectable 1:12 Universal-to-LVPECL Buffer 40-VQFN features• 12 LVPECL Outputsan on-chip multiplexer (MUX) for selecting one of two• Maximum Clock Fre ..
CDCLVP2108RGZT ,Low Jitter, Dual 1:8 Universal-to-LVPECL Buffer 48-VQFN Features 3 DescriptionThe CDCLVP2108 is a highly versatile, low additive1• Dual 1:8 Differential Bu ..
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CL9000 , AM/FM RADIO TRANSISTOR KIT
CLA50E1200HB , High Efficiency Thyristor
CLC001AJE ,Serial Digital Cable Driver with Adjustable OutputsElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
CDCLVP110-CDCLVP110VF-CDCLVP110VFG4-CDCLVP110VFR
1:10 LVPECL/HSTL to LVPECL Clock Driver
LQFP PACKAGE
(TOP VIEW)22212019
VCC
VCC
VCC 18Q3Q4Q4Q5Q5Q6Q6
CDCLVP110Outputs differential clock pair of either LVPECL or HSTL
(selectable) input, (CLK0, CLK1) to ten pairs of
• Fully Compatible With LVECL/LVPECL/HSTLdifferential LVPECL clock (Q0, Q9) outputs with
• Single Supply Voltage Required, ±3.3-Vor minimum skew for clock distribution. The
±2.5-V Supply CDCLVP110 can accept two clock sources into an
• Selectable Clock Input Through CLK_SEL input multiplexer. The CLK0 input accepts either
LVECL/LVPECL input signals, while CLK1 acceptsan
• Low-Output Skew (Typ15 ps) for HSTL input signal when operated under LVPECL
Clock-Distribution Applications conditions. The CDCLVP110is specifically designed
• VBB Reference Voltage Output for for driving 50-Ω transmission lines.
Single-Ended ClockingThe VBB reference voltage output is usedif
• Availableina 32-Pin LQFP Package single-ended input operationis required.In this case
• Frequency Range From DCto 3.5 GHz the VBB pin should be connected to CLK0 and
bypassedto GND
• Pin-to-Pin Compatible With MC100 Series
EP111, ES6111, LVEP111, PTN1111 However, for high-speed
the differential
spacer
spacer The CDCLVP110is characterized for operation from
–40°Cto 85°C.
spacer
spacer
Table1. FUNCTION TABLE
