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CDCLVD110ARHBR-CDCLVD110ARHBT-CDCLVD110AVF-CDCLVD110AVFG4
1-to-10 LVDS Clock Buffer up to 1100MHz with Minimum Skew for Clock Distribution
ASIC
PHY1
PHY8
Oscillator
(156.25
MHz)
156. 25 MHz
CDCLVD110ALVDS Buffer
_SEL
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CDCLVD110ASCAS841D –FEBRUARY 2007–REVISED DECEMBER 2016
CDCLVD110A Programmable Low-Voltage 1:10 LVDS Clock Driver Features Low-Output Skew <30ps (Typical) for Clock-
Distribution Applications Distributes One Differential Clock Inputto LVDS Differential Clock Outputs VCC Range: 2.5V ±5% Typical Signaling Rate Capabilityof Upto
1.1 GHz Configurable Register (SI/CK) Individually Enables
Disables Outputs, Selectable CLK0, CLK0or
CLK1, CLK1 Inputs Full Rail-to-Rail Common-Mode Input Range Receiver Input Threshold: ±100 mV Availablein 32-Pin LQFP and VQFN Package Fail-Safe I/O-Pinsfor VDD=0V (Power Down)
Applications General-Purpose Industrial, Communication and
Consumer Applications
DescriptionThe CDCLVD110A clock driver distributes one pairof
differential LVDS clock inputs (either CLK0or CLK1) 10 pairsof differential clock outputs (Q0to Q9)
with minimum skew for clock distribution. The
CDCLVD110Ais specifically designedto drive 50-Ω
transmission lines.
When the control enableis high (EN= 1), the 10
differential outputs are programmablein that each
output can be individually enabled or disabled
(3-stated) accordingto the first 10 bits loaded into the
shift register. Once the shift registeris loaded, the
last bit selects either CLK0or CLK1 as the clock
input. However, when EN=0, the outputs are not
programmable andall outputs are enabled.
The CDCLVD110A has an improved start-up circuit
that minimizes enabling timein AC- and DC-coupled
systems.
The CDCLVD110Ais characterized for operation
from –40°Cto 85°C.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Application Example
