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CDCLVD110-CDCLVD110VF-CDCLVD110VFR
1-to-10 LVDS clock buffer up to 900MHz with minimum skew for clock distribution
1FEATURES
DESCRIPTION
CDCLVD110SCAS684C–SEPTEMBER 2002–REVISED JANUARY 2008
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Not Recommended for New Designs
PROGRAMMABLE Low-Output <30 ps (Typical) for
Clock-Distribution Applications Distributes Differential Clock Inputto LVDS Clock Outputs VCC rangeV Typical Rate Capabilityof Upto
1.1 GHz Configurable Register (SI/CK) Individually
Enables Outputs, Selectable CLK0,
CLK0 CLK1 Inputs Full Rail-to-Rail Common-Mode Input Range Receiver Threshold ±100 mV Available LQFP Package Fail-Safe for VDD=0V (Power Down)The CDCLVD110 clock driver distributes one pairof differential LVDS clock inputs (either CLK0or CLK1)to10
pairsof clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVD110is
specifically for driving 50-Ω transmission lines. the enableis high (EN= 1), the 10 differential outputs are programmablein that each output can individually (3-stated) accordingto the first 10 bits loaded into the shift register. Once the
shift register the lastbit selects either CLK0or CLK1as the clock input. However, when EN=0, the
outputs are andall outputs are enabled.
Theis characterizedfor operation from –40°Cto 85°C.
Not New Designs. Use CDCLVD110Aasa Replacement.
