CDCL6010RGZTG4 ,1.8V 11-Outputs Clock Multiplier, Distributor, Jitter Cleaner and Buffer 48-VQFN -40 to 85maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
CDCLVD110 ,1-to-10 LVDS clock buffer up to 900MHz with minimum skew for clock distributionELECTRICAL CHARACTERISTICSover recommended operating free-air temperature range (unless otherwise n ..
CDCLVD110ARHBR ,1-to-10 LVDS Clock Buffer up to 1100MHz with Minimum Skew for Clock Distribution 32-VQFN -40 to 85Block Diagram... 1013 Mechanical, Packaging, and Orderable8.3 Feature Description.... 11Information ..
CDCLVD110ARHBT ,1-to-10 LVDS Clock Buffer up to 1100MHz with Minimum Skew for Clock Distribution 32-VQFN -40 to 85Electrical Characteristics....... 511.3 Thermal Considerations.... 186.6 Switching Characteristics: ..
CDCLVD110AVF ,1-to-10 LVDS Clock Buffer up to 1100MHz with Minimum Skew for Clock Distribution 32-LQFP -40 to 85Features 3 DescriptionThe CDCLVD110A clock driver distributes one pair of1• Low-Output Skew <30 ps ..
CDCLVD110AVFG4 ,1-to-10 LVDS Clock Buffer up to 1100MHz with Minimum Skew for Clock Distribution 32-LQFP -40 to 85features a 120-kΩ pulldown resistor, inputThe PowerPAD of the VQFN package is thermally connected t ..
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CL9000 , AM/FM RADIO TRANSISTOR KIT
CLA50E1200HB , High Efficiency Thyristor
CLC001AJE ,Serial Digital Cable Driver with Adjustable OutputsElectrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise ..
CDCL6010RGZT-CDCL6010RGZTG4
1.8V 11-Outputs Clock Multiplier, Distributor, Jitter Cleaner and Buffer
DIVIDER
DIVIDER
SDA/SCL
VCO
PLL1 Bypass
CML Output
5 Differential
CDCL6010
www.ti.com SLLS780B –FEBRUARY 2007–REVISED MARCH 2011
1.8V, 11 Output Clock Multiplier, Distributor, Jitter Cleaner, and Buffer
Checkfor Samples: CDCL6010
1FEATURES •
Integrated LC Oscillator Allows External
Bandwidth Adjustment Single 1.8V Supply PLL Lock Indication•
High-Performance Clock Multiplier, Distributor, Power Consumption: 640mW TypicalJitter Cleaner, and Buffer With11 Outputs Output Enable Control for Each Output•
Low Output Jitter: 400fs RMS SDA/SCL Device Management Interface•
Output Group Phase Adjustment 48-pin QFN (RGZ) Package•
Low-Voltage Differential Signaling (LVDS)
Input, 100Ω Differential On-Chip Termination, •
Industrial Temperature Range: –40°C
to +85°C
30MHzto 319MHz Frequency Range
APPLICATIONS•
Differential Current Mode Logic (CML)
Outputs, 50Ω Single-Ended On-Chip •
Low Jitter Clocking for High-Speed SERDES
Termination, 15MHzto 1.25GHz Frequency •
Jitter Cleaningof SERDES Reference ClocksRange for 1G/10G Ethernet, 1X/2X/4X/10X Fibre One Dedicated Differential CML Output, Channel, PCI Express, Serial ATA, SONET,
Straight PLL and Frequency Divider Bypass CPRI, OBSAI, etc. Two Groupsof Five Outputs Each with •
Upto 1-to-11 Clock Buffering and Fan-out
Independent Frequency Division Ratios;
Optional PLL Bypass Fully Integrated Voltage Controlled Oscillator
(VCO); Supports Wide Output Frequency
Range Output Frequency Derived From VCO
Frequency with Divide Ratiosof1,2,4,5,8,
10, 16, 20, 32, 40, and80 Meets OBSAI RP1 v1.0 Standard and
CPRI v2.0 Requirements
Meets ANSI TIA/EIA-644-A-2001 LVDS
