CDCF2510 ,3.3-V Phase-Lock Loop Clock Drivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CDCF2510 ,3.3-V Phase-Lock Loop Clock Driverblock diagram11G31Y041Y151Y281Y391Y4151Y5161Y617241Y7CLKÁÁÁÁÁÁPLL20131Y8ÁÁÁÁÁÁFBIN211Y923AVCC12FBOU ..
CDCF2510PW ,3.3-V Phase-Lock Loop Clock Drivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CDCF2510PW G4 ,3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 70 SCAS628D − APRIL 1999 − REVISED DECEMBER 2004PW PACKAGE Us ..
CDCF2510PWR ,3.3-V Phase-Lock Loop Clock Drivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CDCF2510PWR. ,3.3-V Phase-Lock Loop Clock Drivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CDCF2510-CDCF2510PW-CDCF2510PW G4-CDCF2510PWR-CDCF2510PWR.
3.3-V Phase-Lock Loop Clock Driver
Operating Frequency 25 MHz to 140 MHz Static Phase Error Distribution at 66 MHzto 133 MHz is ±125 ps Jitter (cyc−cyc) at 66 MHz to 133 MHz Is
|70| ps Available in Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications Distributes One Clock Input to One Bank of
10 Outputs Output Enable Pin to Enable/Disable All 10
Outputs External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input On-Chip Series Damping Resistors No External RC Network Required Operates at 3.3 V
descriptionThe CDCF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDCF2510 operates at a 3.3-V VCC. It also
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50%, independent of the duty cycle at CLK. The outputs can be enabled/disabled with the control (G) input.
When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the
outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDCF2510 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCF2510 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
The CDCF2510 is characterized for operation from 0°C to 85°C.
For application information see the High Speed Distribution Design Techniques for
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with SpreadCC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
VCC
FBIN
1Y0
1Y1
1Y2
GND
GND
1Y4CC
FBOUT
