CDCF2510 ,3.3-V Phase-Lock Loop Clock Drivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CDCF2510 ,3.3-V Phase-Lock Loop Clock Driverblock diagram11G31Y041Y151Y281Y391Y4151Y5161Y617241Y7CLKÁÁÁÁÁÁPLL20131Y8ÁÁÁÁÁÁFBIN211Y923AVCC12FBOU ..
CDCF2510PW ,3.3-V Phase-Lock Loop Clock Drivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CDCF2510PW G4 ,3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 70 SCAS628D − APRIL 1999 − REVISED DECEMBER 2004PW PACKAGE Us ..
CDCF2510PWR ,3.3-V Phase-Lock Loop Clock Drivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CDCF2510PWR. ,3.3-V Phase-Lock Loop Clock Drivermaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CDCF2509PW-CDCF2509PWR
3.3-V Phase-Lock Loop Clock Driver
Operating Frequency 25 MHz to 140 MHz Static Phase Error Distribution at 66 MHz to133 MHz is ±125 ps Jitter (cyc−cyc) at 66 MHz to 133 MHz Is
|70| ps Available in Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs Separate Output Enable for Each Output
Bank External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input On-Chip Series Damping Resistors No External RC Network Required Operates at 3.3 V
descriptionThe CDCF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDCF2509 operates at 3.3 V VCC. It also
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled
or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in
phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDCF2509 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCF2509 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
The CDCF2509 is characterized for operation from 0°C to 85°C.
For application information refer to application reports High Speed Distribution Design Techniques for
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread
1Y0
1Y1
1Y2
GND
GND
1Y3CC
FBOUT
