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CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
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CL431 , Precision Adjustable Shunt Reference
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CDCE72010-CDCE72010RGCR-CDCE72010RGCT
10 Outputs Low Jitter Clock Synchronizer and Jitter Cleaner
CDCE72010
www.ti.com SCAS858C –JUNE 2008–REVISED JANUARY 2012
Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
Checkfor Samples: CDCE72010
1FEATURES •
Wide Charge-Pump Current Range From
200μAto 3mA•
High Performance LVPECL, LVDS, LVCMOS Presets Charge-Pumpto VCC_CP/2 for FastPLL Clock Synchronizer
Center-Frequency Settingof VC(X)O,•
Two Reference Clock Inputs (Primary and Controlled Via the SPI BusSecondary Clock) for Redundancy Support SERDES Startup Mode (Depending on VCXOwith Manualor Automatic Selection
Range)•
Accepts Two Differential Input (LVPECLor Auxiliary Input: Output9 can Serveas 2ndLVDS) References upto 500MHz (or Two
VCXO Inputto Drive All Outputsorto ServeasLVCMOS Inputs upto 250MHz)as PLL
PLL Feedback SignalReference RESETor HOLD Input Pinto Serveas Resetor•
VCXO_IN Clockis Synchronizedto Oneof Two
Hold FunctionsReference Clocks REFERENCE SELECT for Manual Select•
VCXO_IN Frequencies upto 1.5GHz (LVPECL)
Between Primary and Secondary Reference800MHz for LVDS and 250MHz for LVCMOS
ClocksLevel Signaling POWER DOWN (PD)to Put Devicein Standby•
Outputs Canbea Combinationof LVPECL,
ModeLVDS, and LVCMOS (Upto10 Differential
LVPECLor LVDS Outputsor upto20 LVCMOS •
Analog and Digital PLL Lock Indicator
Outputs), Output9 canbe Convertedto an •
Internally Generated VBB Bias Voltages forAuxiliary Inputasa 2nd VC(X)O. Single-Ended Input Signals Output Divideris Selectableto Divide by1,2, •
Frequency Hold-Over Mode Activatedby3,4,5,6,8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36, HOLD Pinor SPI Busto Improve Fail-Safe40, 42, 48, 50, 56, 60, 64, 70,or80 On Each OperationOutput Individually upto Eight Dividers. •
Inputto All Outputs Skew Control(Except for Output0 and9, Output0 Follows •
Individual Skew Control for Each Output withOutput1 Divider and Output9 Follows Output Each Output Divider8 Divider) Packagedina QFN-64 Package•
SPI Controllable Device Setting ESD Protection Exceeds 2kV HBM Control via SPI Industrial Temperature Rangeof –40°C
to 85° Non-Volatile Memory APPLICATIONS Settings without the Need Driver for High-End Telecom •
High Precision PLL Loop
Bandwidth Reference
