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CDCE62005-CDCE62005RGZR-CDCE62005RGZT
5/10 Outputs Clock Generator/Jitter Cleaner with Integrated Dual VCO
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CDCE62005SCAS862G –NOVEMBER 2008–REVISED JULY 2016
CDCE62005 3:5 Clock Generator, Jitter Cleaner with Integrated Dual VCOs Features Superior Performance: Low Noise Clock Generator: 550fs rms typical
(10 kHzto20 MHz Integration Bandwidth),= 100 MHz Low Noise Jitter Cleaner: 2.6ps rms typical
(10 kHzto20 MHz Integration Bandwidth),= 100 MHz
Flexible Frequency Planning: 5 Fully Configurable Outputs: LVPECL, LVDS,
LVCMOS and Special High Swing Output
Modes Unique Dual-VCO Architecture Supportsa
Wide Tuning Range: 1.750 GHzto 2.356 GHz Output Frequency Ranges from 4.25 MHzto
1.175 GHzin Synthesizer Mode Output Frequencyupto 1.5 GHzin Fan-Out
Mode Independent Coarse Skew Controlonall
Outputs
High Flexibility: Integrated EEPROM Determines Device
Configurationat Power-up Smart Input Multiplexer Automatically Switches
Between Oneof Three Reference Inputs 7-mm× 7-mm 48-Pin VQFN Package (RGZ) –40°Cto +85°C Temperature Range
Applications Wireless Infrastructure Switches and Routers Medical Electronics Military and Aerospace Industrial
DescriptionThe CDCE62005 is a high performance clock
generator and distributor featuring low output jitter,a
high degreeof configurability viaa SPI interface, and
programmable start up modes determinedby on-chip
EEPROM. Specifically tailored for clocking data
converters and high-speed digital signals, the
CDCE62005 achieves jitter performance well under1 RMS (10 kHzto20 MHz integration bandwidth).
The CDCE62005 incorporatesa synthesizer block
with partially integrated loop filter,a clock distribution
block including programmable output formats, andan
input block featuring an innovative smart multiplexer.
The clock distribution block includes five individually
programmable outputs that can be configured to
provide different combinations of output formats
(LVPECL, LVDS, LVCMOS). Each output can alsobe
programmedtoa unique output frequency (upto 1.5
GHz) and skew relationship viaa programmable
delay block (note that frequency range depends on
operational mode and output format selected).If all
outputs are configured in single-ended mode (for
example, LVCMOS), the CDCE62005 supports upto
ten outputs. Each output can select oneof four clock
sourcesto condition and distribute including anyof
the three clock inputsor the outputof the frequency
synthesizer. The input block includes two universal
differential inputs which support frequenciesin the
rangeof 40 kHzto 500 MHz and an auxiliary input
that can be configured to connect to an external
crystal viaanon chip oscillator block.
The smart input multiplexer has two modes of
operation, manual and automatic.In manual mode,
the user selects the synthesizer reference via the SPI
interface.In automatic mode, the input multiplexer will
automatically select between the highest priority input
clock available.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe datasheet.
