CDCDLP223PWR ,3.3V Clock Synthesizer for DLP Systems 20-TSSOP -40 to 85maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
CDCDLP223PWRG4 ,3.3V Clock Synthesizer for DLP Systems 20-TSSOP -40 to 85FEATURESCDCDLP223 PIN ASSIGNMENTS• High-Performance Clock Synthesizer• Uses a 20 MHz Crystal Input ..
CDCE18005RGZR ,5/10 Outputs Clock Buffer with Divider 48-VQFN -40 to 85 SCAS863B –NOVEMBER 2008–REVISED NOVEMBER 2012(1)PIN FUNCTIONSPINTYPE DESCRIPTIONNAME QFNVCC_OUT 8, ..
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CDCE421RGER ,Fully Integrated Wide Range Low-Jitter Crystal Oscillator Clock Generator 24-VQFN FEATURES • Differential Low-Voltage PositiveEmitter-Coupled Logic (LVPECL) Output,2• Single 3.3-V S ..
CDCE62002RHBT ,Four Output Clock Generator/Jitter Cleaner with Integrated Dual VCOs 32-VQFN -40 to 85Features Operation• Typical Power Consumption 750 mW at 3.3 V1• Frequency Synthesizer With PLL/VCO ..
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CDCDLP223PW-CDCDLP223PWR-CDCDLP223PWRG4
3.3V Clock Synthesizer for DLP Systems
FEATURESXIN 1 20
XOUT 2
TSSOP20
VSS 3 18
VDD 4 17
20MHZ 5 16
VSS 6 15 7 14
IDO 8 13
SDATA 9 12
SCLK 10 11
IREF
VDD
100MHZ
100MHZ
VSS
VSS
300MHZ
300MHZ
VSS
VDD
TYPICAL APPLICATIONS
DESCRIPTION Synthesizer for DLP™ Systems
CDCDLP223 PIN ASSIGNMENTS•
High-Performance Usesa20 MHz Crystal Inputto Generate
Multiple Output Frequencies Integrated Load20 MHz
Oscillator Reducing All PLL Loop Filter are
Integrated Generates the Following Clocks: REF CLK20 XCG CLK 100 DMD CLK 200-400 Selectable
SSC Very Low Period Jitter Characteristic: ±100
psat20 ±75
psat 100 MHz
Outputs The 100 MHz HCLK output provides the reference
clock for the XDR Clock Generator (CDCD5704).•
Includes Spread-Spectrum Clocking (SSC),Spread-spectrum clocking with 0.5% down spread,
With Down Spread for 100 MHz and Centerwhich reduces Electro Magnetic Interference (EMI),
Spread for 200–400 is applied in the default configuration. The•
HCLK Differential 100 MHz spread-spectrum clocking (SSC)is turned on andoff
and the 200–400 via the serial control interface.•
Operates From The 300 MHz HCLK output providesa 200-400 MHz•
Packagedin TSSOP20 clock signal for the DMD Control Logicof the DLP™
Control ASIC. Frequency selectionin 20 MHz steps•
Characterized for Temperature possible via the serial control interface.
Range -40°CtoSpread-spectrum clocking with ±1.0% or ±1.5%•
ESD Protection center spreadis applied, which can be disabled via•
2000-V Human-Body– the serial control interface
MIL-STD-883, Method 3015 The CDCDLP223 featuresa fail safe start-up circuit,
which enables the PLLs onlyifa sufficient supply
voltageis applied anda stable oscillationis delivered•
Central Clock Generator Systems from the crystal oscillator. After the crystal start-up
time and the PLL stabilization time, all outputs are
ready for use.
The CDCDLP223 performance The CDCDLP223 works froma single 3.3-V supply usein DLP™ andis characterized for operation from –40°Cto usesto generate the 85°C. frequency the frequencies
