CDCD5704PWR ,Rambus XDR(TM) Clock Generator 28-TSSOP 0 to 70SCAS823–DECEMBER 2006The bypass mode routes the input clock REFCLK to the differential output buffe ..
CDCD5704PWRG4 ,Rambus XDR(TM) Clock Generator 28-TSSOP 0 to 70block diagram shows the major components of the CDCD5704, which include a phase-locked loop, abypas ..
CDCDLP223PW ,3.3V Clock Synthesizer for DLP Systems 20-TSSOP -40 to 85features a fail safe start-up circuit,which enables the PLLs only if a sufficient supplyTYPICAL APP ..
CDCDLP223PWR ,3.3V Clock Synthesizer for DLP Systems 20-TSSOP -40 to 85maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
CDCDLP223PWRG4 ,3.3V Clock Synthesizer for DLP Systems 20-TSSOP -40 to 85FEATURESCDCDLP223 PIN ASSIGNMENTS• High-Performance Clock Synthesizer• Uses a 20 MHz Crystal Input ..
CDCE18005RGZR ,5/10 Outputs Clock Buffer with Divider 48-VQFN -40 to 85 SCAS863B –NOVEMBER 2008–REVISED NOVEMBER 2012(1)PIN FUNCTIONSPINTYPE DESCRIPTIONNAME QFNVCC_OUT 8, ..
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CDCD5704PW-CDCD5704PWG4-CDCD5704PWR-CDCD5704PWRG4
Rambus XDR(TM) Clock Generator
www.ti.com
FEATURES
APPLICATIONS
DESCRIPTION High-Speed Clock Support:
Clock Source for XDR Memory
and Redwood Logic Interface Quad (Open-Drain) Differential Spread-Spectrum Compatible Distributedto Minimize EMI Differentialor Single-Ended Reference Clock
Inputof 100 MHzor 133 Serial Interface Features:
Frequency Multiplier, Select Any Oneto
Outputs and Modeof Operation Supports Frequency Multiplication×3, ×4, ×5, ×6, ×8, ×9/2, ×15/2, ×15/4
All PLL Loop Filter Components Are
Integrated Low |Cycle-to-Cycle|of 1–6 40 ps: 300–635 MHz 30 ps: 636–667 MHz PLLs Are Powered Down
Clock (<10 MHz)Is Detectedor VDDIs Below
1.6V Operates From Single 2.5-V Packagedin TSSOP-28 Commercial Temperature Range 0°Cto 70°C XDR Memory Subsystem
InterfaceThe CDCD5704 clock generator
and Redwood logic interface usinga reference
Containedina 28-pin TSSOP
off-the-shelf solution fora broad
The block diagram shows the major components and four differential output lowat the inputof
