CDC706PW ,Custom Programmed 3-PLL Clock Synthesizer / Multiplier / Divider 20-TSSOP FEATURES • Packaged in 20-Pin TSSOP2• High Performance 3:6 PLL Based Clock • Factory Programmable f ..
CDC706PWG4 ,Custom Programmed 3-PLL Clock Synthesizer / Multiplier / Divider 20-TSSOP This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..
CDC706PWR ,Custom Programmed 3-PLL Clock Synthesizer / Multiplier / Divider 20-TSSOP TERMINAL FUNCTIONSTERMINALI/O DESCRIPTIONTSSOP20NAMENO.11, 12, 15,Y0 to Y5 O LVCMOS outputs16, 19, ..
CDC857-2 , 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
CDC857-2DGG , 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
CDC857-2DGG , 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CDC706PW-CDC706PWG4-CDC706PWR
Custom Programmed 3-PLL Clock Synthesizer / Multiplier / Divider 20-TSSOP
S0/CLK_SEL
VCC
GND
CLK_IN0
CLK_IN1
GND
SDATA
SCLOCK CCOUT2
GND CCOUT1
GND
TSSOP20
Pitch 0,65 mm
6.6 x 6.6
VCC
Not Recommended for New Designs
CDC706
www.ti.com...................................................................................................................................... SCAS829B –SEPTEMBER 2006–REVISED FEBRUARY 2008
PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/ MULTIPLIER/ DIVIDER
Checkfor Samples: CDC706
1FEATURES • Packagedin 20-Pin TSSOP High Performance 3:6 PLL Based Clock • Factory Programmable for Customized Default
Synthesizer/ Multiplier/ Divider Settings are Available. ContactTI Sales for
More Details.• User Programmable PLL Frequencies Easy In-Circuit Programming via SMBus Data APPLICATIONSInterface • Wireless Base Stations• Wide PLL Divider Ratio Allows 0-PPM Output • Network Line CardsClock Error • Datacom/ Telecom• Clock Inputs Accepta Crystalora
Single-Ended LVCMOSora Differential Input TERMINAL ASSIGNMENTSignal PACKAGE• Accepts Crystal Frequencies from8 MHz upto (TOP VIEW)54 MHz Accepts LVCMOSor Differential Input
Frequencies upto 200 MHz Two Programmable Control Inputs [S0/S1] for
User Defined Control Signals Six LVCMOS Outputs with Output Frequenciesto 300 MHz LVCMOS Outputs can be Programmed for
Complementary Signals Free Selectable Output Frequency via
Programmable Output Switching Matrix [6x6]
Including 7-Bit Post-Divider for Each Output PLL Loop Filter Components Integrated Low Period Jitter (Typical60 ps) Features Spread Spectrum Clocking (SSC) for Control System Supply
