CDC586PAHR ,3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency OptionsSCAS336E–FEBRUARY 1993–REVISED APRIL 2004The feedback input (FBIN) is used to synchronize the outpu ..
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CDC586-CDC586PAH-CDC586PAHR
3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options
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FEATURES
PAH PACKAGE
(TOP VIEW)16
VCC
4Y3
GND
VCC
4Y2
GND
VCC
4Y1
GND
GND
VCC
3Y3
GND
GND
1Y1
VCC
GND
1Y2
VCC
GND
1Y3
VCC
GND
GND
2Y1
VCC192021
CLKINNC OE5049484752 46
GNDSEL1SEL0AGNDFBINAGNDA
GND
3Y2
GND
2Y3
GNDGND
3Y14342452324252640
GND
2Y2
TESTCLR
SCAS336E–FEBRUARY 1993–REVISED APRIL 2004
PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS Application for Synchronous DRAM,
High-Speed Microprocessor•
Low Output Skew for Clock-Distribution
and Clock-Generation Applications •
TTL-Compatible Inputs and Outputs Operates 3.3-V VCC •
Outputs Drive Parallel 50-Ω Terminated
Transmission Lines•
Distributes One Clock Inputto12
Outputs •
State-of-the-Art EPIC-IIB™ BiCMOS Design
Significantly Reduces Power Dissipation•
Two Select Inputs Configure Upto Nine
Outputs Operateat One-Halfor Double •
Distributed VCC and Ground Pins Reduce
the Input Switching Noise No External RC Network Required •
Packagedin 52-Pin Thin Quad Flat Package External Pin (FBIN)Is Usedto
Synchronize the Outputsto the Clock Inputis low-skew, low-jitter clock driver.It usesa phase-lock loop (PLL)to precisely
