CDC582 ,3.3V PLL Clock Driver with LVPECL Output & LVTTL Outputs with 1/2x, 1x and 2x Frequency Options SCAS446B − JULY 1994 − REVIS ..
CDC582PAH ,3.3V PLL Clock Driver with LVPECL Output & LVTTL Outputs with 1/2x, 1x and 2x Frequency Options SCAS446B − JULY 1994 − REVIS ..
CDC586 ,3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency OptionsSCAS336E–FEBRUARY 1993–REVISED APRIL 2004Output Configuration AOutput configuration A is valid when ..
CDC586 ,3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency OptionsFEATURES • Application for Synchronous DRAM,High-Speed Microprocessor• Low Output Skew for Clock-Di ..
CDC586PAH ,3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency OptionsSCAS336E–FEBRUARY 1993–REVISED APRIL 20043.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
CDC586PAHR ,3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency OptionsSCAS336E–FEBRUARY 1993–REVISED APRIL 2004The feedback input (FBIN) is used to synchronize the outpu ..
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL331-0471-0-10 , SMT Ultra-Miniature Coaxial Connectors-Mating Heights Owing to the Lowest Profile and the Lightest
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CL431 , Precision Adjustable Shunt Reference
CDC582-CDC582PAH
3.3V PLL Clock Driver with LVPECL Output & LVTTL Outputs with 1/2x, 1x and 2x Frequency Options
Two Select Inputs Configure Up to NineOutputs to Operate at One-Half or Double
the Input Frequency No External RC Network Required Application for Synchronous DRAMs Distributed VCC and Ground Pins Reduce
Switching Noise Packaged in 52-Pin Quad Flatpack
PAH PACKAGE
(TOP VIEW)16
VCC
4Y3
GND
VCC
4Y2
GND
VCC
4Y1
GND
GND
VCC
3Y3
GND
GND
1Y1
VCC
GND
1Y2
VCC
GND
1Y3
VCC
GND
GND
2Y1
VCC192021
CLKINCLKINAOE5049484752 46
GNDSEL1SEL0AGNDFBINAGND
GND
3Y2
GND
2Y3
GNDGND
3Y14342452324252640
GND
2Y2
TESTCLR
descriptionThe CDC582 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely
align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN, CLKIN) input
signals. It is specifically designed to operate at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs
configured as half-frequency outputs. The CDC582 operates at 3.3-V VCC.
The feedback input (FBIN) synchronizes the frequency of the output clocks with the input clock
(CLKIN, CLKIN) signals. One of the twelve output clocks must be fed back to FBIN for the PLL to maintain
synchronization between the differential CLKIN and CLKIN inputs and the outputs. The output used as feedback
is synchronized to the same frequency as the clock (CLKIN and CLKIN) inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
