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CDC536-CDC536DBR
3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options
FEATURESAVCC
AGND
CLKIN
SEL
GND
1Y1
VCC
GND
1Y2
VCC
GND
1Y3
VCC
AVCC
AGND
FBIN
TEST
CLR
VCC
2Y1
GND
VCC
2Y2
GND
VCC
2Y3
GND
DESCRIPTION
3.3-V LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS ORDL PACKAGE•
Low-Output for Clock-Distribution and (TOP VIEW)
Clock-Generation Applications Operatesat VCC Distributes One Clock Inputto Six Outputs One Select Input Configures Three Outputsto
Operateat One-Halfor Double the Input
Frequency No External Network Required External Feedback Pin (FBIN)Is Usedto
Synchronize Outputsto the Clock Input Application for Synchronous DRAM,
High-Speed Negative-Edge-Triggered Clear for
Half-Frequency Outputs TTL-Compatible Inputs and Outputs Outputs Drive Parallel-Terminated
Transmission State-of-the-Art EPIC-IIB™ BiCMOS Design
Significantly Power Dissipation Distributed VCC and Ground Pins Reduce
Switching Noise Packagedin 28-Pin Shrink Small
Outline PackageThe CDC536isa low-skew, low-jitter clockIt usesa phase-lock loop (PLL)to precisely
align,in both frequency and phase, the clock output signals the clock input (CLKIN) signal.Itis specifically
designed for use synchronous DRAMs and popular microprocessors operatingat speeds from 50 MHzto
100 MHzor down 25 MHz on outputs configured as half-frequency outputs. The CDC536 operatesat 3.3-V
VCC andis designedto drivea 50-W transmission line.
The feedback input (FBIN)is usedto synchronize the outputin frequency and phaseto the input clock
(CLKIN). Oneof the six output clocks mustbe fed backto FBIN for the PLLto maintain synchronization between
CLKIN and the outputs. The output usedas the feedback pinto the same frequencyas CLKIN.Y outputs can configuredto switchin phase andat the frequencyas CLKIN. The select (SEL) input threeto operateat one-halfor double CLKIN frequency depending on which pinis fed (see1 and 2). All output signal duty cycles are adjustedto 50% independentof the duty input
